SYSTEM IN PACKAGE (SIP) WITH DUAL LAMINATE INTERPOSERS
There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.
1 . A semiconductor device, comprising:
a first preassembled subassembly comprising:
a substrate; and
at least one semiconductor die attached to the substrate; and
a second preassembled subassembly coupled to the first preassembled subassembly and comprising:
an interposer; and
a controller attached to the interposer.
2 . The device of claim 1 , wherein the interposer is adhesively coupled to the at least one semiconductor die.
3 . The device of claim 1 , comprising at least one capacitor attached to the interposer.
4 . The device of claim 1 , wherein the controller is attached such that the controller signals are optimally routed in relation to the semiconductor die.
5 . The device of claim 1 , wherein the interposer consists essentially of bismaleimide triazine.
6 . The device of claim 1 , wherein the interposer consists essentially of silicon.
7 . The device of claim 1 , wherein the interposer consists essentially of ceramic.
8 . The device of claim 1 , wherein the interposer is adhesively coupled to the at least one semiconductor by die attach film.
9 . The device of claim 1 , wherein the interposer is adhesively coupled to the at least one semiconductor die by epoxy.
10 . The device of claim 1 , wherein the at least one semiconductor die comprises two NAND memory dies formed in a stack attached to the substrate.
11 . The device of claim 10 , wherein the stack is a shingle stack.
12 . A semiconductor device, comprising:
a first preassembled subassembly comprising a memory subassembly having at least one memory die; and
a second preassembled subassembly comprising a processor subassembly having a microcontroller.
13 . The device of claim 12 , wherein the memory subassembly comprises a first memory die mounted on a substrate.
14 . The device of claim 13 , wherein the memory subassembly comprises a second memory die mounted on the first memory die.
15 . The device of claim 12 , wherein the memory subassembly comprises at least one NAND memory die.
16 . The device of claim 12 , wherein the processor subassembly comprises a microcontroller mounted on an interposer.
17 . The device of claim 16 , wherein the interposer consists essentially of one of bismaleimide triazine, silicon, or ceramic.
18 . The device of claim 12 , wherein the processor subassembly comprises a plurality of capacitors mounted on an interposer.
19 . The device of claim 12 , wherein the second preassembled subassembly is mounted on top of the first preassembled subassembly.
20 . The device of claim 19 , wherein the second preassembled subassembly is adhesively coupled to the top of the first preassembled subassembly by epoxy.
21 . A semiconductor device, comprising:
a first preassembled subassembly comprising a generic package that has been electrically tested for functionality; and
a second preassembled subassembly coupled to the first preassembled subassembly and comprising an application-specific package that has been electrically tested for functionality, before being coupled to the first preassembled subassembly.
22 . The device of claim 21 , wherein,
the generic package comprises:
a substrate; and
at least one semiconductor die attached to the substrate; and
the application-specific package comprises:
an interposer; and
a controller attached to the interposer.
23 . The device of claim 22 , wherein the interposer is mounted on top of the at least one semiconductor die.
24 . The device of claim 21 , wherein the second preassembled subassembly is coupled to the top of the first preassembled subassembly by an epoxy.
25 . The device of claim 21 , wherein the generic package comprises one or more memory dies.
26 . The device of claim 21 , wherein the application-specific package comprises a microcontroller.