Methods of forming integrated assemblies
View Patent ↗Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
1. A method of forming an integrated assembly, comprising:
providing a structure having first panels of semiconductor material and second panels of insulative material; the first and second panels extending along a first direction, and alternating with one another along a second direction which crosses the first direction;
forming a protective material extending across an upper surface of the structure;
forming trenches extending through the protective material and into the structure;
the trenches extending along the second direction; the trenches forming the protective material and an upper portion of the structure into rails; the rails comprising pillars of the semiconductor material;
forming a coating material which extends over the rails and along interior surfaces of the trenches;
forming a first material over the coating material and within the trenches;
selectively etching the first material relative to the coating material to recess an upper surface of the first material to a first level; first segments of the rails being above said first level;
forming spacers along the first segments of the rails, first portions of the coating material being between the spacers and the first segments of the rails;
selectively etching the first material relative to the coating material and the spacers to recess the first material within the trenches until the upper surface is at a second level;
second segments of the rails being between the first segments and the second level;
second portions of the coating material covering the second segments of the rails; and
forming conductive material within the trenches; the conductive material lining the second segments of the rails.
2. The method of claim 1 comprising utilization of a planarizing process to remove the first material from over the coating material prior to the recessing of the upper surface of the first material to the first level.
3. The method of claim 1 wherein:
the coating material comprises one or more of aluminum oxide, hafnium oxide, zirconium oxide, carbon-doped silicon nitride, boron-doped silicon nitride and carbon-doped silicon dioxide;
the spacers comprise silicon nitride; and
the first material comprises silicon dioxide.
4. The method of claim 3 wherein the protective material comprises silicon nitride.
5. The method of claim 3 wherein the coating material comprises a thickness within a range of from about 10 Å to about 100 Å.
6. The method of claim 1 wherein the second portions of the coating material remain along the second segments of the rails as the conductive material is formed to line said second segments.
7. The method of claim 6 wherein the coating material comprises high-k dielectric material.
8. The method of claim 7 wherein the coating material comprises one or more of aluminum oxide, zirconium oxide and hafnium oxide.
9. The method of claim 1 wherein the second portions of the coating material are removed from the second segments and replaced with dielectric material prior to forming the conductive material within the trenches.
10. The method of claim 9 wherein:
the coating material comprises one or more of aluminum oxide, hafnium oxide, zirconium oxide, carbon-doped silicon nitride, boron-doped silicon nitride and carbon-doped silicon dioxide; and
the dielectric material comprises silicon dioxide.
11. The method of claim 1 wherein some of the semiconductor material of the panels remains as lines passing under the trenches and the pillars, with said lines extending along the first direction.
12. The method of claim 11 wherein said lines of the semiconductor material are incorporated into digit lines; and further comprising:
removing at least portions of the protective material to expose upper regions of the pillars of the semiconductor material; and
coupling charge-storage devices with said exposed upper regions.