IP Library Granted Patent US 11,038,027
Granted Patent B2
US 11,038,027 · App. 16/294,759 · Granted Jun 15, 2021

Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material

Inventors: Kamal M. Karda (Boise, ID); Deepak Chandra Pandey (Uttarakhand, IN); Haitao Liu (Boise, ID); Richard J. Hill (Boise, ID); Guangyu Huang (Boise, ID); Yunfei Gao (Boise, ID); Ramanathan Gandhi (Boise, ID); Scott E. Sills (Boise, ID)
Assignee: Micron Technology, Inc.
H01L29/267H01L27/10805H01L29/0847H01L29/16H01L29/207H01L29/7869H01L29/78675
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Quick Facts
Patent No.
US 11,038,027
App. No.
16/294,759
Granted
Jun 15, 2021
Kind
B2
Abstract

Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Claims (62)

1. An integrated assembly, comprising:

a polycrystalline first semiconductor material;

a second semiconductor material directly adjacent to the polycrystalline first semiconductor material and being of a different composition than the polycrystalline first semiconductor material;

a conductivity-enhancing dopant within the second semiconductor material, the conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline first semiconductor material; and

an electrical gate adjacent to a region of the polycrystalline first semiconductor material and being configured to induce an electric field within said region of the polycrystalline first semiconductor material; the gate not being adjacent to the second semiconductor material.

2. The integrated assembly of claim 1 wherein the second semiconductor material is polycrystalline.

3. The integrated assembly of claim 1 wherein the polycrystalline first semiconductor material comprises silicon, and wherein the second semiconductor material comprises at least one element from Group 13 of the periodic table in combination with at least one element from Group 15 of the periodic table.

4. The integrated assembly of claim 3 wherein the second semiconductor material comprises gallium and phosphorus.

5. The integrated assembly of claim 4 wherein the conductivity-enhancing dopant includes one or more elements from Group 14 of the periodic table.

6. The integrated assembly of claim 4 wherein the conductivity-enhancing dopant includes one or more of silicon, germanium and carbon.

7. The integrated assembly of claim 1 wherein the polycrystalline first semiconductor material comprises silicon, and wherein the second semiconductor material comprises a semiconductor oxide.

8. The integrated assembly of claim 7 wherein the semiconductor oxide includes one or more of indium, zinc, tin and gallium.

9. The integrated assembly of claim 7 wherein the semiconductor oxide includes indium, zinc and gallium.

10. The integrated assembly of claim 9 wherein the conductivity-enhancing dopant includes hydrogen.

11. The integrated assembly of claim 9 wherein the indium, zinc and gallium are each present in the semiconductor oxide to a metal atomic percent, and wherein:

the metal atomic percent of the indium is within a range of from about 16 to about 26;

the metal atomic percent of the gallium is within a range of from about 45 to about 55; and

the metal atomic percent of the zinc is within a range of from about 24 to about 34.

12. The integrated assembly of claim 9 wherein the indium, zinc and gallium are each present in the semiconductor oxide to a metal atomic percent, and wherein:

the metal atomic percent of the indium is within a range of from about 18 to about 24;

the metal atomic percent of the gallium is within a range of from about 47 to about 53; and

the metal atomic percent of the zinc is within a range of from about 26 to about 32.

13. An integrated assembly, comprising:

a polycrystalline semiconductor material having a first side and an opposing second side, and comprising a channel region between the first and second sides;

a first source/drain material adjacent to the first side of the polycrystalline semiconductor material;

a first conductivity-enhancing dopant within the first source/drain material, the first conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material;

a second source/drain material adjacent to the second side of the polycrystalline semiconductor material;

a second conductivity-enhancing dopant within the second source/drain material, the second conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material; and

a transistor gate adjacent to the polycrystalline semiconductor material and not being adjacent to the first and second source/drain materials, and being configured to gatedly couple the first and second source/drain materials through the channel region.

14. The integrated assembly of claim 13 comprising a base under the polycrystalline semiconductor material and supporting the polycrystalline semiconductor material; and wherein the first source/drain material and the second source/drain material are horizontally disposed relative to one another.

15. The integrated assembly of claim 13 comprising a base under the polycrystalline semiconductor material and supporting the polycrystalline semiconductor material; and wherein the first source/drain material and the second source/drain material are vertically disposed relative to one another.

16. The integrated assembly of claim 13 wherein the first and second source/drain materials comprise a same composition as one another.

17. The integrated assembly of claim 16 wherein the first and second conductivity-enhancing dopants comprise a same element as one another.

18. The integrated assembly of claim 16 wherein the first and second conductivity-enhancing dopants comprise different elements relative to one another.

19. The integrated assembly of claim 13 wherein the first and second source/drain materials comprise different compositions relative to one another.

20. The integrated assembly of claim 13 wherein the polycrystalline first semiconductor material comprises silicon; wherein the first and second source/drain materials comprise a same composition as one another; and wherein said same composition comprises at least one element from Group 13 of the periodic table in combination with at least one element from Group 15 of the periodic table.

21. The integrated assembly of claim 20 wherein said same composition comprises gallium and phosphorus.

22. The integrated assembly of claim 21 wherein the first and second conductivity-enhancing dopants include one or more elements from Group 14 of the periodic table.

23. The integrated assembly of claim 13 wherein the polycrystalline first semiconductor material comprises silicon; wherein the first and second source/drain materials comprise a same composition as one another; and wherein said same composition comprises a semiconductor oxide.

24. The integrated assembly of claim 23 wherein the semiconductor oxide includes one or more of indium, zinc, tin and gallium.

25. The integrated assembly of claim 23 wherein the semiconductor oxide includes indium, zinc and gallium.

26. The integrated assembly of claim 25 wherein the conductivity-enhancing dopant includes hydrogen.

27. An integrated assembly, comprising:

a base;

a vertically extending pillar of polycrystalline semiconductor material supported by the base;

the pillar having a bottom side and a top side; the pillar comprising a channel region between the bottom and top sides;

a first source/drain material under the pillar and adjacent to the bottom side;

a first conductivity-enhancing dopant within the first source/drain material, the first conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material;

a second source/drain material over the pillar and adjacent to the top side;

a second conductivity-enhancing dopant within the second source/drain material, the second conductivity-enhancing dopant being a neutral-type dopant relative to the polycrystalline semiconductor material;

a transistor gate adjacent to the polycrystalline semiconductor material, the transistor gate being absent from along the first and second source/drain materials, and being configured to gatedly couple the first and second source/drain materials through the channel region; and

a charge-storage device coupled with one of the first and second source/drain materials.

28. The integrated assembly of claim 27 wherein the polycrystalline semiconductor material, first source/drain material, second source/drain material and transistor gate are comprised by an access transistor; wherein the access transistor and the charge-storage device are comprised by a memory cell; wherein the transistor gate is coupled with a wordline; and wherein the other of the first and second source/drain materials is coupled with a digit line.

29. The integrated assembly of claim 28 wherein the memory cell is one of many substantially identical memory cells within a memory array; wherein the wordline is one of many wordlines within the memory array; wherein the digit line is one of many digit lines within the memory array; and wherein each of the memory cells is uniquely addressed through one of the digit lines in combination with one of the wordlines.

30. The integrated assembly of claim 29 wherein the memory array is within a tier; the tier being within a vertically-stacked arrangement of tiers and being over at least one other of the tiers within the vertically-stacked arrangement.

31. The integrated assembly of claim 27 wherein the polycrystalline first semiconductor material comprises silicon; wherein the first and second source/drain materials comprise a same composition as one another; and wherein said same composition comprises at least one element from Group 13 of the periodic table in combination with at least one element from Group 15 of the periodic table.

32. The integrated assembly of claim 31 wherein said same composition comprises gallium and phosphorus.

33. The integrated assembly of claim 32 wherein the first and second conductivity-enhancing dopants include one or more elements from Group 14 of the periodic table.

34. The integrated assembly of claim 27 wherein the polycrystalline first semiconductor material comprises silicon; wherein the first and second source/drain materials comprise a same composition as one another; and wherein said same composition comprises a semiconductor oxide.

35. The integrated assembly of claim 34 wherein the semiconductor oxide includes one or more of indium, zinc, tin and gallium.

36. The integrated assembly of claim 34 wherein the semiconductor oxide includes indium, zinc and gallium.

37. The integrated assembly of claim 36 wherein the conductivity-enhancing dopant includes hydrogen.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2019
From: KARDA, KAMAL M.; PANDEY, DEEPAK CHANDRA; LIU, HAITAO; HILL, RICHARD J.; HUANG, GUANGYU; GAO, YUNFEI; GANDHI, RAMANATHAN; SILLS, SCOTT E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048523/0611 →