IP Library Granted Patent US 10,763,186
Granted Patent B2
US 10,763,186 · App. 16/237,111 · Granted Sep 1, 2020

Package cooling by coil cavity

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Quick Facts
Patent No.
US 10,763,186
App. No.
16/237,111
Granted
Sep 1, 2020
Kind
B2
Abstract

A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

Claims (69)

1. A method of manufacturing a semiconductor device, the method comprising:

surrounding at least two sides of a die package with a sacrificial member;

encapsulating the die package and sacrificial member in an encapsulant material; and

removing the sacrificial member via chemically etching, melting, dissolving, vaporizing, and/or shattering the sacrificial member.

2. The method of claim 1 , further comprising:

providing a substrate comprising a first surface and a second surface opposite the first surface; and

connecting the die package to the first surface of the substrate.

3. The method of claim 2 , further comprising connecting a second die package to the first surface of the substrate.

4. The method of claim 1 , wherein the sacrificial member is a coil surrounding the die package on at least three sides.

5. The method of claim 1 , wherein surrounding at least two sides of the die package comprises surrounding all lateral sides of the die package with the sacrificial member.

6. The method of claim 5 , wherein the sacrificial member is a coil.

7. The method of claim 1 , further comprising pumping fluid through a cavity in the encapsulant formed by the removal of the sacrificial member.

8. The method of claim 1 , wherein removing the sacrificial member results in a first opening to an exterior of the encapsulant material and a second opening to the exterior of the encapsulant material, wherein the first opening is in fluid communication with the second opening through the encapsulant material.

9. The method of claim 8 , further comprising:

connecting a fluid pump to the first opening such that the fluid pump is in fluid communication with the first opening; and

pumping fluid into the encapsulant material through the one of first opening or the second opening and out from the encapsulant material through the other of the first opening or the second opening.

10. The method of claim 8 , further comprising:

connecting a heat exchanger to the first opening or to the second opening; and

pumping the fluid from the heat exchanger to the first opening or to the second opening.

11. A semiconductor device assembly comprising:

a first die package comprising:

a bottom side;

a top side; and

lateral sides extending between the top and bottom sides;

an encapsulant material encapsulating the first die package; and

a cooling cavity in the encapsulant material, the cooling cavity comprising:

a first opening;

a second opening; and

an elongate channel extending from the first opening to the second opening;

wherein:

the elongate channel surrounds at least two of the lateral sides of the first die package;

the elongate channel is configured to accommodate a cooling fluid; and

wherein the first opening and the second opening are the only openings of the cooling cavity, and wherein the elongate channel of the cooling cavity is a single channel between the first opening and the second opening without splits, forks, and dead ends.

12. The semiconductor device assembly of claim 11 , further comprising:

a fluid pump in fluid communication with at least one of the first opening and the second opening; and

a fluid line between the fluid pump and at least one of the first opening and the second opening;

wherein the fluid pump and elongate channel form at least a part of a closed fluid system.

13. The semiconductor device assembly of claim 12 , further comprising a heat exchanger in fluid communication with the fluid pump and either the first opening or the second opening.

14. The semiconductor device assembly of claim 11 , wherein the elongate channel surrounds all lateral sides of the first die package.

15. The semiconductor device assembly of claim 11 , wherein the elongate channel has a helical shape surrounding all lateral sides of the first die package.

16. The semiconductor device assembly of claim 11 , wherein both the first opening and the second opening are through a top surface of the encapsulant material.

17. The semiconductor device assembly of claim 11 , further comprising a second die package comprising a bottom side, a top side, and lateral sides extending between the top surface and the bottom surface, wherein the elongate channel of the cooling cavity surrounds at least two lateral sides of the second die package.

18. The semiconductor device assembly of claim 17 , further comprising a substrate comprising a first surface and a second surface opposite the first surface, wherein both the first die package and the second die package are connected to the first surface of the substrate.

19. The semiconductor device assembly of claim 18 , wherein the top side of the first die package faces away from the substrate, and wherein the first die package includes a heat sink connected to the top side of the first die package.

20. The semiconductor device assembly of claim 19 , further comprising a thermal interface material between the heat sink and the top side of the first die package.

21. The semiconductor device assembly of claim 19 , wherein the cooling cavity is not in fluid communication with the heat sink.

22. The semiconductor device assembly of claim 11 , further comprising a substrate comprising a first surface and a second surface opposite the first surface, wherein the first die package is connected to the first surface of the substrate.

23. The semiconductor device assembly of claim 22 , wherein the top side of the first die package faces away from the substrate, and wherein the first die package includes a heat sink connected to the top side of the first die package.

24. The semiconductor device assembly of claim 23 , wherein the cooling cavity is not in fluid communication with the heat sink.

25. The semiconductor device assembly of claim 11 , wherein the first die package is a component of a graphics card.

26. The semiconductor device assembly of claim 11 , wherein a height of the first die package, as measured from the bottom side to the top side, is 750 microns or less.

27. A semiconductor device assembly comprising:

a first die package comprising:

a bottom side;

a top side; and

lateral sides extending between the top and bottom sides;

an encapsulant material encapsulating the first die package; and

a cooling cavity in the encapsulant material, the cooling cavity comprising:

a first opening;

a second opening; and

an elongate channel extending from the first opening to the second opening;

wherein:

the elongate channel surrounds at least two of the lateral sides of the first die package;

the elongate channel is configured to accommodate a cooling fluid; and

wherein the elongate channel has a helical shape or serpentine shape surrounding all lateral sides of the first die package.

28. The semiconductor device assembly of claim 27 , wherein both the first opening and the second opening are through a top surface of the encapsulant material.

29. The semiconductor device assembly of claim 27 , further comprising a substrate comprising a first surface and a second surface opposite the first surface, wherein the first die package is connected to the first surface of the substrate.

30. The semiconductor device assembly of claim 29 , wherein the top side of the first die package faces away from the substrate, and wherein the first die package includes a heat sink connected to the top side of the first die package.

31. The semiconductor device assembly of claim 30 , wherein the cooling cavity is not in fluid communication with the heat sink.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2019
From: BAYLESS, ANDREW M; HUANG, WAYNE H; FAY, OWEN R
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050882/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →