IP Library Granted Patent US 10,672,470
Granted Patent B1
US 10,672,470 · App. 16/209,352 · Granted Jun 2, 2020

Performing a test of memory components with fault tolerance

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,672,470
App. No.
16/209,352
Granted
Jun 2, 2020
Kind
B1
Abstract

An indication that a test resource of a test platform has failed can be received. The test resource can be associated with performing a portion of a test of memory components. A characteristic of the test resource that failed can be determined. Another test resource of the test platform can be identified based on the characteristic of the test resource that failed. The portion of the test of memory components can be performed based on the another test resource of the test platform.

Claims (44)

1. A method comprising:

receiving an indication that a test resource of a test platform has failed, wherein the test resource is associated with performing a portion of a test of memory components;

determining a characteristic of the test resource that failed;

identifying another test resource of the test platform based on the characteristic of the test resource that failed; and

performing, by a processing device, the portion of the test of memory components based on the another test resource of the test platform.

2. The method of claim 1 , wherein test resource comprises a memory component, and wherein the characteristic of the test resource corresponds to a usage characteristic of the memory component of the test resource.

3. The method of claim 2 , wherein the identifying of the another test resource of the test platform based on the characteristic of the test resource that failed comprises determining that a usage characteristic of another memory component of the another test resource matches the usage characteristic of the memory component of the test resource.

4. The method of claim 1 , wherein the test corresponds to a sequence of operations performed at the memory component, and wherein the performing of the portion of the test of memory components based on the another test resource comprises:

determining a last performed operation of the sequence of operations that was performed at the test resource before the failure of the test resource; and

performing one or more additional operations subsequent to the last performed operation of the sequence of operations at another memory component of the another test resource.

5. The method of claim 1 , further comprising:

receiving results of the portion of the test of memory components performed at the test resource before the failure of the test resource; and

receiving additional results of the portion of the test of memory components performed at the another test resource after the failure of the test resource.

6. The method of claim 1 , wherein the characteristic of the test resource indicates a number of prior operations that have been performed at the test resource.

7. The method of claim 1 , wherein the characteristic of the test resource indicates a prior temperature condition that has been applied to the test resource.

8. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

receive an indication that a first test resource of a test platform that has been performing a first portion of a test of a plurality of memory components has failed;

determine whether a second test resource of the test platform that has been performing a second portion of the test of the plurality of memory components is dependent on the first test resource of the test platform; and

in response to determining that the second test resource is dependent on the first test resource, pause a performance of the second portion of the test by the second test resource of the test platform.

9. The system of claim 8 , wherein to determine whether the second test resource is dependent on the first test resource, the processing device is further to:

determine whether a result of the first portion of the test performed by the first test resource is used by the second test resource to perform the second portion of the test.

10. The system of claim 9 , wherein the result of the first portion of the test specifies a particular temperature condition that is to be applied to a particular memory component of the second test resource.

11. The system of claim 9 , wherein the result of the first portion of the test specifies a particular operation that is to be performed at a particular memory component of the second test resource.

12. The system of claim 9 , wherein the result of the first portion of the test corresponds to a behavior of a particular memory component included in the first test resource in response to a particular operation performed on the particular memory component at a particular temperature condition.

13. The system of claim 8 , wherein the processing device is further to:

receive an indication that the failure of the first test resource has been resolved; and

provide an instruction to resume the performance of the second portion of the test by the second test resource of the test platform.

14. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

receiving an indication that a test resource of a test platform has failed, wherein the test resource is associated with performing a portion of a test of memory components;

determining a characteristic of the test resource that failed;

identifying another test resource of the test platform based on the characteristic of the test resource that failed; and

performing the portion of the test of memory components based on the another test resource of the test platform.

15. The non-transitory computer readable medium of claim 14 , wherein test resource comprises a memory component, and wherein the characteristic of the test resource corresponds to a usage characteristic of the memory component of the test resource.

16. The non-transitory computer readable medium of claim 15 , wherein the identifying of the another test resource of the test platform based on the characteristic of the test resource that failed comprises determining that a usage characteristic of another memory component of the another test resource matches the usage characteristic of the memory component of the test resource.

17. The non-transitory computer readable medium of claim 14 , wherein the characteristic of the test resource indicates a number of prior operations that have been performed at the test resource.

18. The non-transitory computer readable medium of claim 14 , wherein the test corresponds to a sequence of operations performed at the memory component, and wherein to perform the portion of the test of memory components based on the another test resource, the operations further comprise:

determining a last performed operation of the sequence of operations that was performed at the test resource before the failure of the test resource; and

performing one or more additional operations subsequent to the last performed operation of the sequence of operations at another memory component of the another test resource.

19. The non-transitory computer readable medium of claim 14 , wherein the characteristic of the test resource indicates a prior temperature condition that has been applied to the test resource.

20. The non-transitory computer readable medium of claim 14 , the operations further comprising:

receiving results of the portion of the test of memory components performed at the test resource before the failure of the test resource; and

receiving additional results of the portion of the test of memory components performed at the another test resource after the failure of the test resource.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2018
From: THIRUVENGADAM, ASWIN; PARTHASARATHY, SIVAGNANAM; SCOBEE, DANIEL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047670/0274 →