Slit oxide and via formation techniques
Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps.
1. A method, comprising:
forming a hole through a deck of a memory device to expose a conductive via located below the deck, wherein the deck of the memory device comprises a plurality of memory cell stacks;
depositing, in the hole, a dielectric material, wherein the dielectric material is separated from a nearest memory cell stack of the plurality of memory cell stacks by a distance that is less than a pitch of the plurality of memory cell stacks;
removing a portion of the dielectric material from the hole to expose the conductive via located below the deck; and
depositing, in the hole, a conductive material to extend the conductive via through the deck.
2. The method of claim 1 , further comprising:
forming a set of trenches through the deck to create an electrically floating portion of the deck, wherein the conductive via extends through the electrically floating portion of the deck.
3. The method of claim 2 , wherein the electrically floating portion of the deck comprises one or more electrically floating access line segments coupled with one or more electrically floating memory cell stacks.
4. The method of claim 3 , wherein the dielectric material is in contact with at least one of the one or more electrically floating access line segments.
5. The method of claim 2 , further comprising:
depositing, in the set of trenches, a second dielectric material to at least partially fill the set of trenches.
6. The method of claim 5 , further comprising:
depositing, above the second dielectric material in the set of trenches, a second conductive material.
7. The method of claim 1 , wherein forming the hole through the deck comprises:
severing an access line included in the deck.
8. The method of claim 1 , further comprising:
forming a second hole through the deck;
depositing, in the second hole, the dielectric material;
removing a second portion of the dielectric material from the second hole; and
depositing, in the second hole, the conductive material to form a second conductive via that is electrically isolated from any conductive via located below the deck.
9. A method, comprising:
identifying a deck of a memory device, the deck comprising an access line coupled with memory cell stacks;
forming a set of trenches through the deck to create a portion of the deck that comprises electrically floating segments of the access line coupled with electrically floating memory cell stacks; and
depositing, in the set of trenches, a dielectric material for electrically isolating the electrically floating segments of the access line from other segments of the access line in the deck.
10. The method of claim 9 , further comprising:
depositing, above the dielectric material in the set of trenches, a conductive material.
11. The method of claim 9 , further comprising:
forming a hole through the portion of the deck to expose a conductive via located below the electrically floating segments of the access line.
12. The method of claim 11 , further comprising:
depositing, in the hole, a second dielectric material to partially fill the hole;
removing a portion of the second dielectric material from the hole to expose the conductive via located below the electrically floating segments of the access line; and
depositing, in the hole, a second conductive material to extend the conductive via through the deck.
13. A method, comprising:
forming a hole through a deck of a memory device comprising a plurality of memory cell stacks to expose a conductive via located below the deck;
depositing, in the hole, a dielectric material, wherein the dielectric material is in contact with at least one memory cell stack of the plurality of memory cell stacks;
removing a portion of the dielectric material from the hole to expose the conductive via located below the deck;
depositing, in the hole, a conductive material to extend the conductive via through the deck; and
forming a set of trenches through the deck to create an electrically floating portion of the deck, wherein the conductive via extends through the electrically floating portion of the deck.
14. The method of claim 13 , wherein the electrically floating portion of the deck comprises one or more electrically floating access line segments coupled with one or more electrically floating memory cell stacks.
15. The method of claim 14 , wherein the dielectric material is in contact with at least one of the one or more electrically floating access line segments.
16. The method of claim 13 , further comprising:
depositing, in the set of trenches, a second dielectric material to at least partially fill the set of trenches.
17. The method of claim 16 , further comprising:
depositing, above the second dielectric material in the set of trenches, a second conductive material.
18. A method, comprising:
forming a hole through a deck of a memory device comprising a plurality of memory cell stacks to expose a conductive via located below the deck, wherein forming the hole through the deck comprises severing an access line included in the deck;
depositing, in the hole, a dielectric material, wherein the dielectric material is in contact with at least one memory cell stack of the plurality of memory cell stacks;
removing a portion of the dielectric material from the hole to expose the conductive via located below the deck; and
depositing, in the hole, a conductive material to extend the conductive via through the deck.
19. A method, comprising:
forming a hole through a deck of a memory device comprising a plurality of memory cell stacks to expose a conductive via located below the deck;
depositing, in the hole, a dielectric material, wherein the dielectric material is in contact with at least one memory cell stack of the plurality of memory cell stacks;
removing a portion of the dielectric material from the hole to expose the conductive via located below the deck;
depositing, in the hole, a conductive material to extend the conductive via through the deck;
forming a second hole through the deck;
depositing, in the second hole, the dielectric material;
removing a second portion of the dielectric material from the second hole; and
depositing, in the second hole, the conductive material to form a conductive via that is electrically isolated from any conductive via located below the deck.