IP Library Granted Patent US 11,574,659
Granted Patent B2
US 11,574,659 · App. 16/127,850 · Granted Feb 7, 2023

Parallel access to volatile memory by a processing device for machine learning

Inventor: Gil Golov (Backnang, DE)
Assignee: Micron Technology, Inc.
G11C7/10G06N3/02G06N3/04G06N3/08G06N20/00G11C7/22
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,574,659
App. No.
16/127,850
Granted
Feb 7, 2023
Kind
B2
Abstract

A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel.

Claims (37)

1. A system, comprising:

a processing device;

a plurality of memory regions configured to store data used by the processing device; and

at least one controller coupled to the plurality of memory regions and configured to:

read data from a first memory region of the plurality of memory regions, including reading first data from the first memory region, the first data for use by the processing device in processing associated with machine learning; and

write data, received as output data from a computer model, to a second memory region of the plurality of memory regions, including writing second data to the second memory region so that the second data can be accessed sequentially when subsequently read from the second memory region by the processing device for use by the computer model;

wherein reading the first data and writing the second data are performed in parallel.

2. The system of claim 1 , wherein the at least one controller comprises a respective controller used for read or write access to each of the memory regions.

3. The system of claim 1 , wherein the first memory region is used in a continuous burst mode when the first data is read.

4. The system of claim 3 , wherein the second memory region is used in a continuous burst mode when the second data is written.

5. The system of claim 1 , wherein:

the first data is used as an input to a neural network;

the second data is an output from the neural network; and

during the processing associated with machine learning, the first memory region operates in a read-only mode, and the second memory region operates in a write-only mode.

6. The system of claim 1 , wherein each of the plurality of memory regions is a bank in a volatile memory.

7. The system of claim 6 , wherein the volatile memory is a dynamic random access memory.

8. The system of claim 1 , wherein the processing device, the plurality of memory regions, and the at least one controller are disposed on the same chip or die, and the processing device uses the first data as an input to the computer model for machine learning.

9. The system of claim 8 , wherein the computer model is a neural network.

10. The system of claim 8 , wherein the processing device provides the second data as an output from the computer model.

11. A method, comprising:

reading, by a first controller and in response to a request from a processing device, first data from a first memory region of a plurality of memory regions;

performing, by the processing device, processing associated with a neural network, wherein the first data is an input to the neural network, and second data is provided as an output from the neural network;

structuring, by the processing device, the second data for storage in a second memory region of the plurality of memory regions so that the second data can be accessed sequentially for use by the neural network when subsequently read from the second memory region; and

writing, by a second controller, the second data to the second memory region, wherein writing the second data is performed in parallel with reading the first data.

12. The method of claim 11 , further comprising reading, by the second controller, the second data from the second memory region, wherein the second data is accessed sequentially from the second memory region for use as an input to the neural network.

13. The method of claim 11 , further comprising reading, by a third controller, third data from a third memory region of the plurality of memory regions, wherein reading the second data and reading the third data are performed in parallel, and wherein the third data is used as an input to the neural network.

14. The method of claim 11 , wherein the processing associated with the neural network comprises training the neural network using data stored in the first memory region.

15. The method of claim 11 , further comprising:

receiving, by the processing device, data from a sensor;

wherein the processing associated with the neural network comprises using the data from the sensor as an input to the neural network.

16. The method of claim 11 , further comprising determining, by the processing device, a type of the neural network, wherein structuring the second data for storage in the second memory region is based on the determined type.

17. The method of claim 11 , wherein the first memory region is used in a continuous burst mode when reading the first data, and the second memory region is used in a continuous burst mode when writing the second data.

18. The method of claim 11 , wherein, during the processing associated with the neural network, the first memory region operates in a read-only mode, and the second memory region operates in a write-only mode.

19. A non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform a method, the method comprising:

reading first data from a first bank of a dynamic random access memory;

performing processing associated with a neural network, wherein the first data is an input to the neural network, and second data is provided as an output by the neural network; and

writing the second data to a second bank of the dynamic random access memory so that the second data can be accessed sequentially when subsequently read from the second memory region by the processing device for use by the neural network, wherein writing the second data is performed in parallel with reading the first data.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 067140/0277 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2018
From: GOLOV, GIL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046841/0226 →
Continuity (1)
Related Publication 20200082852A1 · Mar 12, 2020