Virtual address table
View Patent ↗The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory.
1. A system, comprising:
a host comprising a processor; and
a memory device coupled to the host, wherein the host is configured to:
generate an object file comprising:
multiple instructions each comprising a number of arguments; and
respective address tables corresponding to the multiple instructions and each comprising a number of indexed address elements each corresponding to a virtual address of a respective one of the number of arguments;
populate the address elements of the address tables with virtual addresses corresponding to the number of arguments; and
translate the virtual addresses corresponding to the number of arguments to physical locations in a memory array of the memory device prior to providing an instruction dispatch block to the memory device.
2. The system of claim 1 , wherein the processor is configured to generate the object file via execution of a compiler.
3. The system of claim 1 , further comprising a translation component.
4. The system of claim 3 , further comprising a channel controller, and wherein the translation component is a component of the channel controller.
5. The system of claim 4 , wherein the channel controller is located on a same die as the processor.
6. The system of claim 3 , wherein the translation component includes a memory management unit.
7. The system of claim 1 , wherein at least one of the multiple instructions comprises a performed in memory device (PIMD) instruction comprising an intrinsic function recognized by a compiler executable by the processor.
8. The system of claim 1 , wherein the processor is configured to initiate an application corresponding to the object file.
9. The system of claim 1 , wherein the multiple instructions comprise performed in memory device (PIMD) instructions whose arguments target the address tables, and wherein the object file also comprises a number of non-PIMD instructions whose arguments target registers of the processor.
10. A system, comprising:
a host; and
a memory device coupled to the host, wherein the host is configured to:
execute a compiler to generate an object file comprising:
multiple instructions each comprising a number of arguments; and
respective address tables corresponding to the multiple instructions and each comprising a number of indexed address elements each corresponding to a virtual address of a respective one of the number of arguments;
populate, at runtime, the address elements of the address tables with virtual addresses corresponding to the number of arguments such that a populated address table exists on the host; and
prior to providing an instruction dispatch block to the memory device, translate the virtual addresses corresponding to the number of arguments to physical locations in a memory array of the memory device.
11. The system of claim 10 , wherein the host is coupled to the memory device via a bus, and wherein the host comprises a processor and a channel controller.
12. The system of claim 10 , wherein the host is coupled to the memory device via a bus, and wherein the host comprises a translation component and a memory management unit.
13. The system of claim 12 , wherein the memory management unit is a component of the translation component.
14. The system of claim 12 , wherein the translation component is a component of the channel controller.
15. The system of claim 10 , wherein the channel controller is external to the host.
16. A system, comprising:
a memory device configured to execute performed in memory device (PIMD) instructions; and
a host coupled to the memory device and comprising:
a processor;
a channel controller;
a translation component; and
a memory management component; and
wherein the host is configured to:
compile an object file, the object file comprising:
multiple instructions each comprising a number of arguments; and
respective address tables corresponding to the multiple instructions and each comprising a number of indexed address elements each corresponding to a virtual address of a respective one of the number of arguments; and
execute the object file by:
populating, at runtime, the address elements of the address tables with virtual addresses corresponding to the number of arguments; and
translating the virtual addresses corresponding to the number of arguments to physical locations in a memory array of the memory device prior to providing an instruction dispatch block to the memory device for execution.
17. The system of claim 16 , wherein the memory device is also configured to execute non-PIMD instructions whose arguments target registers of the processor.
18. The system of claim 16 , wherein the translation component is a component of the channel controller.
19. The system of claim 18 , wherein the memory management component is a component of the translation component.
20. The system of claim 16 , wherein the processor and channel controller are on a same die which is separated from a die on which the memory device resides.