Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
1. A device comprising:
a first region having a semiconductor material of a first type;
gates located along a length of the first region, each of the gates being separated from the first region by a respective charge storage structure, the gates including a first gate and a second gate, the first gate located at a first portion of the first region, and the second gate located at a second portion of the first region;
a second region having a semiconductor material of the first type;
a third region located between and contacting the first region and the second region, the third region having a semiconductor material of a second type, the first portion of the first region located between the third region and the second portion of the first region; and
a conductive material contacting the third region and surrounding the third region, wherein part of the first region, part of the second region, and part of the third region form part of a bipolar junction transistor.
2. The device of claim 1 , wherein the first type includes n-type silicon.
3. The device of claim 2 , wherein the second type includes p-type silicon.
4. The device of claim 1 , wherein the first type includes p-type silicon.
5. The device of claim 4 , wherein the second type includes n-type silicon.
6. A device comprising:
a first conductive material;
a conductive contact contacting the first conductive material;
a first region contacting the conductive contact, the first region having a semiconductor material of a first type;
memory cell structures located along a length of the first region, the memory cell structures including a first charge storage structure and a second charge storage structure, the first charge storage structure located at a first portion of the first region, and the second charge storage structure located at a second portion of the first region;
a second region having a semiconductor material of the first type;
a third region located between and contacting the first region and the second region, the third region having a semiconductor material of a second type, the first portion of the first region located between the third region and the second portion of the first region; and
a second conductive material contacting the third region and surrounding the third region, wherein part of the first region, part of the second region, and part of the third regions form part of a bipolar junction transistor; and
a third conductive material contacting the second conductive material.
7. The device of claim 6 , wherein each of the memory cell structures includes polysilicon material.
8. The device of claim 6 , wherein each of the memory cell structures includes nitride material.
9. The device of claim 6 , wherein each of the first and second charge storage structures is a polysilicon material.
10. The device of claim 6 , wherein each of the first and second charge storage structures is nitride material.
11. A device comprising:
a first region having a semiconductor material of a first type;
memory cell structures located along a length of the first region, the memory cell structures including a first charge storage structure and a second charge storage structure, the first charge storage structure located at a first portion of the first region, and the second charge storage structure located at a second portion of the first region;
a second region having a semiconductor material of the first type;
a third region located between and contacting the first region and the second region, the third region having a semiconductor material of a second type different from the first type, the first portion of the first region located between the third region and the second portion of the first region;
a first conductive material contacting the third region;
a first additional region having a semiconductor material of the first type;
additional memory cell structures located along a length of the first additional region, the additional memory cell structures including a first additional charge storage structure and a second additional charge storage structure, the first additional charge storage structure located at a first portion of the first additional region, and the second additional charge storage structure located at a second portion of the additional first region;
a second additional region having a semiconductor material of the first type;
a third additional region located between and contacting the first additional region and the second additional region, the third additional region having a semiconductor material of the second type, and the first portion of the first additional region located between the third additional region and the second portion of the first additional region; and
a second conductive material contacting the third additional region, wherein the second conductive material contacting the first conductive material.
12. The device of claim 11 , further comprising:
a first gate and a second gate, the first gate located at the first portion of the first region, and the second gate located at the second portion of the first region.
13. The device of claim 12 , further comprising:
a first additional gate and a second additional gate, the first additional gate located at the first portion of the first additional region, and the second additional gate located at the second portion of the first additional region.
14. The device of claim 13 , wherein the first gate contacts the first additional gate, and the second gate contacts the second additional gate.
15. The device of claim 11 , wherein the first type includes n-type silicon.
16. The device of claim 15 , wherein the second type includes p-type silicon.
17. The device of claim 11 , wherein the first type includes p-type silicon.
18. The device of claim 17 , wherein the second type includes n-type silicon.
19. The device of claim 11 , wherein each of the first and second charge storage structures and each of the first and second additional charge storage structures is a polysilicon material.
20. The device of claim 11 , wherein each of the first and second charge storage structures and each of the first and second additional charge storage structures is nitride material.