IP Library › Granted Patent US 10,615,114

Granted Patent B2

US 10,615,114 · App. 16/269,687 · Granted Apr 7, 2020

Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays

Inventor: Durai Vishak Nirmal Ramaswamy (Boise, ID)

Assignee: Micron Technology, Inc.

H01L23/5225 G11C5/02 G11C5/10 G11C5/025

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Quick Facts

Patent No.: US 10,615,114
App. No.: 16/269,687
Granted: Apr 7, 2020
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.

Claims (70)

1. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines;

in a second level above the first level, rows of transistor wordlines;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines; and

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines; and

another of said first array directly above said first array.

2. The array of claim 1 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

3. The array of claim 1 wherein the memory cells individually have a total of only one transistor and a total of only one capacitor.

4. The array of claim 1 wherein one of the first-level conductive shield lines is laterally between every immediately-adjacent of the first-level digitlines.

5. The array of claim 1 wherein the first-level columns of digitlines and the first-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the first-level digitlines have one of the first-level conductive shield lines laterally there-between and such that every immediately-adjacent of the first-level conductive shield lines have one of the first-level digitlines laterally there-between.

6. The array of claim 1 wherein one of the fifth-level conductive shield lines is laterally between every immediately-adjacent of the fifth-level digitlines.

7. The array of claim 1 wherein the fifth-level columns of digitlines and the fifth-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the fifth-level digitlines have one of the fifth-level conductive shield lines laterally there-between and such that every immediately-adjacent of the fifth-level conductive shield lines have one of the fifth-level digitlines laterally there-between.

8. The array of claim 1 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

9. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines;

in a second level above the first level, rows of transistor wordlines;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines;

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines; and

the memory cells individually having a total of only one transistor and a total of only one capacitor; and

another of said first array directly above said first array, the first level of the another of said first array being directly above the fifth level of the first array.

10. The array of claim 9 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

11. The array of claim 9 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

12. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines;

in a second level above the first level, rows of transistor wordlines;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines;

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines; and

the memory cells individually having a total of only one transistor and a total of only one capacitor; and

another of said first array directly above said first array, the fifth level of the first array being the first level of the another of said first array such that the alternating columns of digitlines and conductive shield lines therein are shared by the first array and the another of said first array.

13. The array of claim 12 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

14. The array of claim 12 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

15. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;

in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines;

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;

the memory cells individually having a total of only one transistor and a total of only one capacitor, the transistors individually comprising a channel region, the transistor wordlines being laterally over opposing sides of individual of the channel regions in the row direction; and

another of said first array directly above said first array.

16. The array of claim 15 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

17. The array of claim 15 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

18. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;

in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines;

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;

another of said first array directly above said first array.

19. The array of claim 18 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

20. The array of claim 18 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

21. An array of memory cells individually comprising a capacitor and a transistor, comprising:

a first array comprising:

in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;

in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;

in a third level above the second level, rows and columns of capacitors;

in a fourth level above the third level, rows of transistor wordlines;

in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;

the memory cells individually having a total of only one transistor and a total of only one capacitor, the transistors individually comprising a channel region, the transistor wordlines being laterally surrounding all sides of individual of the channel regions; and

another of said first array directly above said first array.

22. The array of claim 21 wherein the digitlines of the another of said first array are directly above the shield lines of said first array.

23. The array of claim 21 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.

Assignments (4)

RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019

From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT

To: MICRON TECHNOLOGY, INC.

Reel/Frame 051041/0317 →

RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019

From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT

To: MICRON TECHNOLOGY, INC.

Reel/Frame 050724/0392 →