IP Library Granted Patent US 11,101,015
Granted Patent B2
US 11,101,015 · App. 16/222,295 · Granted Aug 24, 2021

Multi-dimensional usage space testing of memory components

Inventors: Aswin Thiruvengadam (Folsom, CA); Sivagnanam Parthasarathy (Carlsbad, CA); Preston Thomson (Boise, ID)
Assignee: Micron Technology, Inc.
G11C29/38G11C29/36G06F11/263
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Quick Facts
Patent No.
US 11,101,015
App. No.
16/222,295
Granted
Aug 24, 2021
Kind
B2
Abstract

A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.

Claims (51)

1. A method comprising:

generating a target vector representing a usage parameter corresponding to a test of a memory component;

assigning a test sample to the target vector;

randomly selecting a set of path variables to associate with the test sample;

executing, by a processing device, a test process of the test using the test sample in accordance with the set of path variables to generate a test result; and

identifying a failure associated with the test result.

2. The method of claim 1 , further comprising:

reserving one or more memory components as the test sample.

3. The method of claim 1 , further comprising:

generating a plurality of different target vectors, each of the different target vectors representing a different usage parameter.

4. The method of claim 3 , further comprising:

assigning a set of one or more test samples to each of the plurality of different target vectors.

5. The method of claim 4 , further comprising:

generating a set of randomly selected path variables to associate with each of the set of one or more test samples.

6. The method of claim 1 , further comprising:

receiving, via a connection with a test process corresponding to the test sample, feedback information comprising the test result.

7. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

generate a plurality of target vectors corresponding to a plurality of a first type of usage parameters of a memory component;

assign a first test sample to a target vector of the plurality of target vectors;

generate a first set of randomly selected path variables for the first test sample;

execute a first test process of the test using the first test sample in accordance with the first set of randomly selected path variables and the target vector to generate a first test result; and

identify a failure associated with the first test result.

8. The system of claim 7 , wherein the first type of usage parameters comprises at least one of: a count of writes, a count of reads, a block type, a partial program rate, an interrupt type, a time between writes, a time between reads, a block erase type, a read page fraction, an interrupt rate, a time between writes and reads, a block type rate, or an interrupt time.

9. The system of claim 7 , wherein the first set of path variables comprises one or more usage parameters exhibiting change during operation of a corresponding memory component.

10. The system of claim 7 , the processing device is further to:

assign a second test sample to the target vector of the plurality of target vectors;

generate a second set of randomly selected path variables for the second test sample; and

execute a second test process of the test using the second test sample in accordance with the second set of randomly selected path variables and the target vector to generate a second test result.

11. The system of claim 7 , the processing device is further to:

reserve a memory component of a test resource as the first test sample; and

assign connection information to the first test process executed using the first test sample.

12. The system of claim 7 , the processing device is further to:

receive, from the first test process via a connection established using the connection information, feedback information comprising the first test result.

13. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

generating a target vector representing a usage parameter corresponding to a test of a memory component;

assigning a test sample to the target vector;

randomly selecting a set of path variables to associate with the test sample;

executing a test using the test sample in accordance with the set of path variables to generate a test result; and

identifying a failure associated with the test result.

14. The non-transitory computer readable medium of claim 13 , wherein the operations further comprise:

reserving one or more memory components as the test sample.

15. The non-transitory computer readable medium of claim 13 , wherein the operations further comprise:

generating a plurality of different target vectors, each of the different target vectors representing a different usage parameter.

16. The non-transitory computer readable medium of claim 15 , wherein the operations further comprise:

assigning a set of one or more test samples to each of the plurality of different target vectors.

17. The non-transitory computer readable medium of claim 16 , wherein the operations further comprise:

generating a set of randomly selected path variables to associate with each of the set of one or more test samples.

18. The non-transitory computer readable medium of claim 13 , wherein the operations further comprise:

receiving, via a connection with a test process corresponding to the first test sample, feedback information comprising the test result.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2018
From: THIRUVENGADAM, ASWIN; PARTHASARATHY, SIVAGNANAM; THOMSON, PRESTON
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047804/0231 →