Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
1. A semiconductor device assembly comprising:
a substrate having a first side and a second side, the substrate having a plurality of complementary metal-oxide-semiconductor circuits;
a first semiconductor device connected directly to the first side of the substrate;
a second semiconductor device connected directly to the first side of the substrate, wherein the substrate is configured to enable the first semiconductor device and the second semiconductor device to communicate directly with each other through the substrate;
a redistribution layer positioned on the second side of the substrate; and
a plurality of interconnects connected to the redistribution layer, wherein the redistribution layer enables a connection between the plurality of interconnects with at least the first semiconductor device.
2. The semiconductor device assembly of claim 1 , wherein the plurality of complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the first semiconductor device and the second semiconductor device.
3. The semiconductor device assembly of claim 2 , wherein the plurality of complementary metal-oxide-semiconductor circuits provides logic to control data transfer between the first semiconductor device and the second semiconductor device.
4. The semiconductor device assembly of claim 1 , wherein the substrate is a silicon substrate configured to connect the first semiconductor device and the second semiconductor device to the redistribution layer.
5. The semiconductor device assembly of claim 4 , wherein the first semiconductor device is a processing unit.
6. The semiconductor device assembly of claim 5 , wherein the processing unit further comprises a graphics processing unit (GPU) or a central processing unit (CPU).
7. The semiconductor device assembly of claim 6 , wherein the second semiconductor device is a memory device.
8. The semiconductor device assembly of claim 7 , wherein the memory device further comprises a high bandwidth memory device.
9. The semiconductor device assembly of claim 1 , further comprising a third semiconductor device connected directly to the first side of the silicon substrate, wherein the third semiconductor device is a memory device and wherein the first semiconductor device and the third semiconductor device communicate with each other through the silicon substrate.
10. The semiconductor device assembly of claim 1 , wherein the first side of the substrate comprises back end of line (BEOL) layers and wherein the first and second semiconductor devices are connected directly to the BEOL layers.
11. The semiconductor device assembly of claim 10 , comprising a plurality of vias through the substrate, wherein the plurality of vias electrically connect the BEOL layers to the redistribution layer.
12. A semiconductor device assembly comprising:
a silicon substrate having a first side and a second side, the silicon substrate having complementary metal-oxide-semiconductor circuits and the first side includes back end of line (BEOL) layers;
a graphics processing unit (GPU) or central processing unit (CPU) connected directly to the BEOL layers of the silicon substrate; and
a plurality of memory devices connected directly to the BEOL layers of the silicon substrate, wherein the GPU or CPU and the plurality of memory devices communicate directly with each other through the silicon substrate.
13. The semiconductor device assembly of claim 12 , wherein the complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the GPU or CPU and the plurality of memory devices.
14. The semiconductor device assembly of claim 12 , wherein the plurality of memory devices comprises at least two high bandwidth memory devices.
15. The semiconductor device assembly of claim 12 , comprising a redistribution layer on the second side of the silicon substrate, the redistribution layer being connected to a plurality of solder balls.
16. The semiconductor device assembly of claim 15 , further comprising at least one via through the silicon substrate, the at least one via electrically connecting the BEOL layers to the redistribution layer.