IP Library Granted Patent US 11,074,198
Granted Patent B2
US 11,074,198 · App. 16/134,387 · Granted Jul 27, 2021

Key management in computer processors

Inventor: Steven Jeffrey Wallach (Dallas, TX)
Assignee: Micron Technology, Inc.
G06F12/1408G06F12/1018G06F12/1475G06F21/602G06F21/71G06F21/79H04L9/0861H04L9/0894G06F2212/1052
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Quick Facts
Patent No.
US 11,074,198
App. No.
16/134,387
Granted
Jul 27, 2021
Kind
B2
Abstract

Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a secure zone configured to store keys and an unscrambled zone configured to operate on unscrambled data. The processor can convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data. Another processor may also be coupled with the memory, but can be prevented from accessing the unscrambled data in the unscrambled zone.

Claims (38)

1. A computer system, comprising:

a memory configured to store scrambled data;

a first processor coupled with the memory, the first processor having:

a secure zone configured to store keys; and

an unscrambled zone configured to operate on unscrambled data, wherein the first processor is configured to convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data;

a second processor coupled with the memory, wherein the second processor is prevented from accessing the unscrambled data in the unscrambled zone of the first processor; and

a storage device configured to store the scrambled data, wherein the scrambled data in the memory is loaded from the storage device;

wherein the first processor includes a scrambled zone having an internal cache configured to store the scrambled data, and the second processor is provided with access to the scrambled zone via a cache coherence protocol.

2. The computer system of claim 1 , wherein the unscrambled zone includes a memory address register configured to store a virtual memory address; and the first processor is configured to unscramble the scrambled data in response to an instruction using the virtual memory address to load the scrambled data for operations within the unscrambled zone.

3. The computer system of claim 2 , wherein the unscrambled zone includes an execution unit configured to perform the operations on a data item located at the virtual memory address stored in the memory address register.

4. The computer system of claim 2 , wherein the virtual memory address includes a field containing an object identifier; and the first processor is configured to retrieve an unscramble key based on the object identifier.

5. The computer system of claim 4 , wherein the secure zone includes a key store; and the first processor is configured to hash at least the object identifier into an index and use the index to retrieve an entry from the key store; wherein the unscramble key is based on the entry.

6. The computer system of claim 5 , wherein the entry includes at least one of an indication of whether an object represented by the object identifier is scrambled, a type of scrambling of the object, a scramble key corresponding to the unscramble key, or the unscramble key, or any combination thereof.

7. The computer system of claim 5 , wherein the secure zone further includes a collision chain configured to identify different entries for different object identifiers that are hashed into the same index; and the first processor is configured to identify the entry using the collision chain.

8. The computer system of claim 4 , wherein the first processor is further configured to store at least one of a key for a virtual machine hosted in the computer system, a key for a user account, or a key for a running process, or any combination thereof.

9. The computer system of claim 4 , wherein the scrambled data is protected via an object key and at least one of a virtual machine key, a user key, or a process key, or any combination thereof, wherein the object key is associated with the object among a plurality of objects, the virtual machine key is associated with a virtual machine among a plurality of virtual machines, the user key is associated with a user account among a plurality of user accounts; and the process key is associated with a running process among a plurality of running processes.

10. The computer system of claim 9 , wherein the first processor is configured to generate the unscramble key for the scrambled data from:

the object key retrieved from the secure zone using the object identifier; and

the at least one of the virtual machine key, the user key, or the process key, or any combination thereof.

11. The computer system of claim 9 , wherein the first processor is configured to generate the unscramble key through scrambling the object key according to the at least one of the virtual machine key, the user key, or the process key, or any combination thereof.

12. The computer system of claim 1 , wherein the first processor and the second processor are packaged in a same integrated circuit chip.

13. A method, comprising:

storing scrambled data in a memory of a computer system, wherein the scrambled data in the memory is loaded from the storage device;

storing keys in a secure zone of a first processor coupled with the memory in the computer system;

converting, by the first processor, the scrambled data into unscrambled data in an unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data; and

operating, by the first processor in the unscrambled zone, on the unscrambled data;

wherein a second processor coupled with the memory in the computer system is prevented from accessing the unscrambled data in the unscrambled zone of the first processor,

wherein the first processor includes a scrambled zone having an internal cache configured to store the scrambled data, and the second processor is provided with access to the scrambled zone via a cache coherence protocol.

14. The method of claim 13 , further comprising:

loading the scramble data from the memory into the processor according to a virtual memory address, wherein the virtual memory address contains an object identification; and

obtaining an unscramble key from the secure zone using the object identification.

15. The method of claim 14 , wherein the unscramble key is specific for a user for which the first processor is executing the instructions.

16. A computer processor, comprising:

a memory providing a scrambled zone configured to store scrambled data;

a secure zone configured to store keys; and

an unscrambled zone configured to operate on unscrambled data, wherein the computer processor is configured to convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data;

wherein the unscrambled data is an instruction, an address, or an operand of an instruction;

wherein the scrambled data and the unscrambled data have a same set of bits having different orders from one another.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2018
From: WALLACH, STEVEN JEFFREY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046901/0112 →