IP Library Granted Patent US 10,796,899
Granted Patent B2
US 10,796,899 · App. 16/235,398 · Granted Oct 6, 2020

Silicon doping for laser splash blockage

Inventor: Angelo Oria Espina (Taichung, TW)
Assignee: Micron Technology, Inc.
H01L21/02129H01L21/268H01L21/78
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Quick Facts
Patent No.
US 10,796,899
App. No.
16/235,398
Granted
Oct 6, 2020
Kind
B2
Abstract

Semiconductor devices having silicon doping for laser splash protection, along with associated methods and systems, are disclosed herein. In one embodiment, a semiconductor device includes a silicon layer and a circuitry layer with a plurality of semiconductor devices. A doped silicon region is formed on a front side of the silicon layer upon which the circuitry layer is deposited. The doped silicon region is positioned under the circuitry layer. The doped silicon region has a dopant concentration of at least 10 15 cm −3 .

Claims (16)

1. A method of dicing a silicon substrate, the method comprising:

applying a mask to a front side of the silicon substrate, wherein the mask includes one or more openings exposing one or more regions to be doped;

introducing dopant atoms at the one or more regions;

diffusing the dopant atoms into the one or more regions using a rapid thermal procession until the one or more regions have a dopant concentration of at least 10 15 cm −3 ;

forming an active layer of circuitry at the front side of the substrate;

stealth dicing the substrate from a back surface thereof using laser irradiation to cleave one or more portions of a silicon lattice of the substrate, the one or more portions being vertically aligned with the one or more regions; and

back-grinding the back surface of the substrate to mechanically separate adjacent semiconductor dice from the substrate on opposing sides of the one or cleaved more portions of the silicon lattice of the substrate,

wherein the dopant concentration of the one or more regions is configured to absorb a laser splash from the stealth dicing or to reflect the laser splash away from the active layer of circuitry.

2. The method of claim 1 , wherein the mask aligns with scribe lines between a plurality of semiconductor devices of a circuitry layer.

3. The method of claim 1 , wherein the mask aligns with a plurality of semiconductor devices of a circuitry layer.

4. The method of claim 1 , wherein the mask is only applied to a surrounding border adjacent to a plurality of scribe lines.

5. The method of claim 1 , wherein the dopant concentration comprises boron impurities.

6. The method of claim 1 , wherein the dopant concentration comprises phosphorous impurities.

7. The method of claim 1 , wherein the dopant concentration is based on a desired index of refraction for the doped silicon region.

8. The method of claim 1 , wherein the dopant concentration is based on a desired light transmissivity for the doped silicon region.

9. The method of claim 1 , wherein the dopant concentration is based on an ability of the doped silicon region absorb a laser splash containing a wavelength of about 1000-1342 nm.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: ESPINA, ANGELO ORIA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047903/0977 →
Cited By (2)
US 12,412,771 US 12,622,196