Memory cell structures

1. A memory cell, comprising:

an interface dielectric on a semiconductor;

a first storage dielectric on the interface dielectric;

a tunnel dielectric on the first storage dielectric such that the interface dielectric is between the semiconductor and the tunnel dielectric and in contact with the first storage dielectric;

a charge trap on the tunnel dielectric, such that the tunnel dielectric is beneath the charge trap and between and in direct contact with the first storage dielectric and the charge trap;

a second storage dielectric on the charge trap;

a blocking dielectric on the second storage dielectric; and

a control gate on the blocking dielectric.

2. The memory cell of claim 1 , further comprising an interface metallic between the blocking dielectric the control gate.

3. The memory cell of claim 1 , wherein the first storage dielectric and the second storage dielectric are of the same material.

4. The memory cell of claim 1 , wherein the first storage dielectric comprises nano-particles.

5. The memory cell of claim 1 , wherein the first storage dielectric is to store at least a portion of charges from the interface dielectric.

6. The memory cell of claim 1 , wherein the tunnel dielectric is to accelerate charges from the interface dielectric and/or from the first storage dielectric to the charge trap.

7. The memory cell of claim 1 , wherein the interface dielectric comprises silicon oxynitride, the first storage dielectric comprises injector-silicon-rich nitride, the tunnel dielectric comprises hafnium lanthanum oxynitride, the charge trap comprises gallium nitride, second storage dielectric comprises injector-silicon-rich nitride, and the blocking dielectric comprises hafnium lanthanum oxynitride or hafnium lanthanum oxynitride and aluminum oxide.

8. The memory cell of claim 1 , wherein a greater energy is needed to free charge from the charge trap than from the second storage dielectric.

9. The memory cell of claim 1 , wherein a conduction energy of the tunnel dielectric is to decrease with increasing distance away from the first storage dielectric during programming.

10. A method of forming a memory cell, comprising:

forming an interface dielectric on a semiconductor;

forming a first storage dielectric on the interface dielectric;

forming a tunnel dielectric on the first storage dielectric such that the interface dielectric is between the semiconductor and the tunnel dielectric and in contact with the first storage dielectric;

forming a charge trap on the tunnel dielectric such that the tunnel dielectric is beneath the charge trap and between and in direct contact with the first storage dielectric and the charge trap;

forming a second storage dielectric on the charge trap;

forming a blocking dielectric on the second storage dielectric; and

forming a control gate on the blocking dielectric.

11. The method of claim 10 , further comprising forming an interface metallic between the blocking dielectric the control gate.

12. The method of claim 10 , wherein forming the first storage dielectric and the second storage dielectric comprises forming the first storage dielectric and the second storage dielectric from the same material.

13. The method of claim 10 , wherein forming second storage dielectric adjacent to the charge trap comprises forming the second storage dielectric such that the charge trap is between second storage dielectric and the tunnel dielectric.

14. A memory cell, comprising:

a dielectric stack on a semiconductor; and

a control gate on the dielectric stack such that the dielectric stack is between the control gate and the semiconductor;

wherein the dielectric stack comprises:

an interface dielectric on the semiconductor;

a first storage dielectric on the interface dielectric;

a tunnel dielectric on the first storage dielectric such that the interface dielectric is between the semiconductor and the tunnel dielectric and in contact with the first storage dielectric;

a charge trap on the tunnel dielectric such that the tunnel dielectric is beneath the charge trap and between and in direct contact with the first storage dielectric and the charge trap; and

a second storage dielectric on the charge trap such that the charge trap is between second storage dielectric and the tunnel dielectric.

15. The memory cell of claim 14 , wherein the tunnel dielectric is in direct physical contact with the first storage dielectric and the charge trap.

16. The memory cell of claim 14 , wherein the first and second storage dielectrics each comprise an injector dielectric.

17. The memory cell of claim 16 , wherein the dielectric stack comprises an silicon oxynitride interface dielectric between and in direct physical contact with the first storage dielectric and the semiconductor.

18. The memory cell of claim 14 , wherein the tunnel dielectric comprises hafnium lanthanum oxynitride.

19. The memory cell of claim 14 , further comprising an interface metallic between the dielectric stack and the control gate.

20. The memory cell of claim 14 , wherein

the dielectric stack further comprises a hafnium lanthanum oxynitride blocking dielectric in direct physical contact with the second storage dielectric; and

the memory cell further comprises a tantalum nitride interface metallic between and in direct physical contact with the hafnium lanthanum oxynitride blocking dielectric and the control gate.