Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command. buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.
1. An apparatus comprising:
an input/output (I/O) circuit configured to provide or receive data responsive to four I/O clock signals;
a clock divider circuit configured to receive a first clock signal and to frequency divide the first clock signal to output four phase clock signals; and
a data clock timing circuit configured to, responsive to the four phase clock signals, provide the four I/O clock signals to the I/O circuit at a first frequency while in a first mode, and to provide the four I/O clock signals to the I/O circuit at a second frequency, while in a second mode.
2. The apparatus of claim 1 , wherein the input/output circuit comprises:
a read data output circuit configured, when activated by a read command, to receive a plurality of read data bits in parallel and to provide the plurality of read data bits in series responsive to the four I/O clock signals; and
a write data input circuit configured, when activated by a write command, to receive a plurality of write data bits in series and to provide the plurality of write data bits in parallel responsive to the four I/O clock signals.
3. The apparatus of claim 1 , further comprising:
a read command buffer configured to buffer a read command responsive to a third clock signal and configured to provide the read command responsive to a fourth clock signal, wherein the input/output circuit comprises a read data output circuit configured,
when activated by a read command, to receive a plurality of read data bits in parallel and to provide the plurality of read data bits in series responsive to the four I/O clock signals, and
wherein the data clock timing circuit is configured to provide the fourth clock signal having the second frequency in the first and second modes.
4. The apparatus of claim 1 ,
wherein the data clock timing circuit is further configured to provide, responsive to the four phase clock signals, a buffer clock signal at the second frequency in the first and second modes.
5. The apparatus of claim 4 , wherein the first clock signal has the first frequency and the buffer clock signal has the second frequency.
6. The apparatus of claim 4 , wherein the first mode is a double data rate mode and the second mode is a quad data rate mode.
7. The apparatus of claim 1 , wherein the dock divider circuit is configured to provide the four phase clock signals having a 90 degree phase relationship with each other.
8. The apparatus of claim 1 , further comprising:
a write command buffer configured to buffer a write command responsive to a third clock signal and configured to provide the write command responsive to a fourth clock signal,
wherein the input/output circuit comprises a write data input circuit configured, when activated by a write command, to receive write data in series and to provide write data in parallel responsive to the four I/O dock signals, and
wherein the data clock timing circuit is configured to provide e fourth clock signal having the second frequency in the first and second modes.
9. The apparatus of claim 1 , further comprising a read command buffer configured to buffer read commands responsive to command and address clock signals and provide the read commands responsive to a third clock signal,
wherein the third dock signal has the second frequency in both the first and second modes.
10. The apparatus of claim 1 , further comprising a write command buffer configured to buffer write commands responsive to command and address clock signals and provide the write commands to the input/output circuit responsive to a third clock signal,
wherein the third dock signal has the second frequency in both the first and second modes.
11. The apparatus of claim 1 , wherein the first frequency is greater than the second frequency.
12. The apparatus of claim 1 , wherein the second frequency is one-half of the first frequency.
13. An apparatus comprising:
an input/output circuit;
a clock divider circuit configured to receive a first clock signal and output at least one clock signal, wherein the a clock divider circuit is configured to output four phase clock signals, the at least one clock signal is included in the four phase clock signals, and
a data clock timing circuit configured to, responsive to the at least one clock signal, provide a second clock signal at one of first and second frequencies to the input/output circuit, wherein the data clock timing circuit is configured to, responsive to the four phase clock signals, provide input/output (I/O) clock signals to the input/output circuit, the second clock signal included in the input/output clock signals.
14. The apparatus of claim 13 , wherein the four phase clock signals provided by the clock divider circuit include four phase divided dock signals having the second frequency.
15. The apparatus of claim 14 , wherein the first frequency is greater than the second frequency.
16. The apparatus of claim 13 , wherein the data clock timing circuit is further configured to, responsive to the received four phase clock signals, provide a buffer clock signal at the second frequency.