Semiconductor recess formation
Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
1. A method comprising:
patterning a silicon material within a semiconductor structure using a wet etch dilution of an elevated temperature of acid and water to remove bulges on the semiconductor structure;
patterning the silicon material within the semiconductor structure using a wet etch dilution of a room temperature acid and water and a surface modification chemistry; and
patterning materials within the semiconductor structure with a reducing strip to decrease the semiconductor structure resistance and remove the surface modification chemistry.
2. The method of claim 1 , further comprising having the temperature of the elevated temperature dilution being a range of 60 to 75 degrees Celsius.
3. The method of claim 1 , wherein patterning the silicon material within the semiconductor structure using the wet etch dilution of the room temperature acid and water and the surface modification chemistry further comprises:
having the temperature of the wet etch dilution of the room temperature acid and water being a range of 20 to 25 degrees Celsius; and
etching the nitride material within the semiconductor structure using a wet etch with a ratio of approximately 300 parts of deionized water to approximately 1 part hydrofluoric acid.
4. The method of claim 1 , wherein patterning the nitride material within the semiconductor structure using the wet etch dilution of the elevated temperature of acid and water further comprises using a dilution of an elevated temperature dilution of approximately 2000 parts of deionized water to approximately 1 part acid for patterning the nitride material within the semiconductor structure.
5. The method of claim 1 , further comprising beginning performing the room temperature wet etch dilution beginning after the completion of the elevated temperature wet etch dilution.
6. The method of claim 1 , further comprising shaping the semiconductor structure into a straight profile with an increased area to deposit capacitor materials.
7. A method comprising:
etching a silicon material within a semiconductor structure using a wet etch dilution of an elevated temperature of approximately 2000 parts of deionized water to approximately 1 part hydrofluoric acid;
etching the silicon material within the semiconductor structure using a room temperature wet etch of approximately 300 parts of deionized water to approximately 1 part hydrofluoric acid and surface modification chemistry; and
performing a reducing strip on materials within the semiconductor structure to decrease the semiconductor structure resistance and remove the surface modification chemistry.
8. The method of claim 7 , wherein etching the silicon material within the semiconductor structure comprises etching a high aspect ratio semiconductor structure having silicon layers and a metal layer.
9. The method of claim 8 , further comprising forming the nitride layer over the etched silicon and metal layer.
10. The method of claim 8 , wherein etching the semiconductor structure comprises etching the high aspect ratio semiconductor structure with a first silicon layer as a semiconductor.
11. The method of claim 8 , further comprising etching the semiconductor structure having tungsten as the metal layer.
12. The method of claim 8 , wherein etching the silicon material within the semiconductor structure comprises etching the high aspect ratio semiconductor structure with a second silicon layer as a dielectric.
13. The method of claim 7 , wherein the reducing strip comprises Oxygen and Hydrogen (O 2 /H 2 ).