IP Library Granted Patent US 10,685,718
Granted Patent B2
US 10,685,718 · App. 16/173,557 · Granted Jun 16, 2020

Dynamic delay of NAND read commands

Inventor: David Aaron Palmer (Boise, ID)
Assignee: Micron Technnology, Inc.
G11C16/26G06F3/0611G06F3/0659G06F3/0679G06F12/0246G06F13/1642G11C16/32G06F2212/1024
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Quick Facts
Patent No.
US 10,685,718
App. No.
16/173,557
Granted
Jun 16, 2020
Kind
B2
Abstract

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.

Claims (59)

1. A method for increasing a probability of a parallel read within a memory die of a non-volatile memory device, the method comprising:

at a controller of the memory device, performing operations comprising:

receiving a first host read command requesting data stored on a first plane of a die of the memory device;

determining that a host read command queue does not contain a second host read command for a second plane of the die, the host read command queue queueing host read commands, the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

2. The method of claim 1 , wherein the delay time period is variable and is determined based upon a depth of the host read command queue.

3. The method of claim 2 , comprising:

increasing the delay time period responsive to a decrease in the host read command queue.

4. The method of claim 1 , wherein the method further comprises:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die delaying execution of the third host read command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

5. The method of claim 1 , wherein causing execution of the host read command and the second host read command comprises combining the commands.

6. The method of claim 1 , wherein causing execution of the host read command and the second host read command comprises canceling the timer.

7. The method of claim 1 , wherein the memory device is a NAND memory device.

8. The method of claim 1 , wherein the method further comprises:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue contains a fourth host read command requesting data stored on the second plane; and

responsive to determining that the host read command queue contains the fourth host read command, causing parallel execution of the third and fourth host read command without a delay period.

9. A memory device comprising:

a NAND die, the die comprising a first and second plane; and

a controller configured to perform operations comprising:

receiving a first host read command requesting data stored on a first plane of the die of the memory device;

determining that a host read command queue does not contain a second host read command for the second plane of the die, the host read command queue queueing host read commands the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

10. The memory device of claim 9 , wherein the delay time period is variable and wherein the operations comprise determining a delay time period value based upon a depth of the host read command queue.

11. The memory device of claim 10 , wherein the operations further comprise:

increasing the delay time period responsive to a decrease in the host read command queue.

12. The memory device of claim 9 , wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die delaying execution of the third host read command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

13. The memory device of claim 9 , wherein the operations of causing execution of the host read command and the second host read command comprises combining the commands.

14. The memory device of claim 9 , wherein the operations of causing execution of the host read command and the second host read command comprises canceling the timer.

15. The memory device of claim 9 , wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue contains a fourth host read command requesting data stored on the second plane; and

responsive to determining that the host read command queue contains the fourth host read command, causing parallel execution of the third and fourth host read command without a delay period.

16. A machine-readable medium storing instructions, which when executed by a controller, cause the controller to perform operations comprising:

receiving a first host read command requesting data stored on a first plane of a die of a non-volatile memory device;

determining that a host read command queue does not contain a second host read command for a second plane of the die, the host read command queue queueing host read commands the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

17. The machine-readable medium of claim 16 , wherein the delay time period is variable and wherein the operations comprise determining a delay time period value based upon a depth of the host read command queue.

18. The machine-readable medium of claim 17 , wherein the operations further comprise:

increasing the delay time period responsive to a decrease in the host read command queue.

19. The machine-readable medium of claim 16 , wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die, delaying execution of the third host read command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

20. The machine-readable medium of claim 16 , wherein the operations of causing execution of the host read command and the second host read command comprises combining the commands.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2019
From: PALMER, DAVID AARON
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050360/0990 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Cited By (1)
US 12,205,653