Memory including search logic

1. A memory comprising:

a memory array comprising a plurality of pages;

a page buffer comprising:

first registers to store data read from a page of the memory array;

second registers to store a user pattern;

compare logic to compare the data stored in the first registers to the user pattern stored in the second registers; and

third registers to store the comparison results; and

search logic configured to identify addresses of the memory array where the comparison results stored in the third registers indicate a match between the data read from the page and column of the memory array and the user pattern,

wherein the first registers are loaded with data from a following page of the memory array concurrently with the search logic identifying addresses indicating a match in a previous page of the memory array.

2. The memory of claim 1 , wherein the compare logic comprises XOR logic.

3. The memory of claim 1 , wherein the second registers store multiple repeating copies of the user pattern in response to a number of bits of the user pattern being less than a number of bits of a page of the memory array.

4. The memory of claim 1 , further comprising:

address registers to store the identified addresses.

5. The memory of claim 4 , further comprising:

an input/output interface to load the user pattern into the second registers and to output the identified addresses from the address registers.

6. The memory of claim 5 , further comprising:

control logic configured to output the identified addresses stored in the address registers via the input/output interface once each page of the plurality of pages of the memory array has been read.

7. The memory of claim 5 , further comprising:

control logic configured to output the identified addresses stored in the address registers via the input/output interface once a single address is identified.

8. The memory of claim 5 , further comprising:

control logic configured to output the identified addresses stored in the address registers via the input/output interface once a predefined number of addresses are identified.

9. The memory of claim 1 , wherein the search logic comprises an address counter to track the addresses of the data read from the memory array.

10. A memory comprising:

a plurality of NAND memory arrays, each NAND memory array of the plurality of NAND memory arrays comprising:

a page buffer comprising:

first registers to store a page of data read from that NAND memory array;

second registers to store a user pattern;

XOR logic configured to XOR the data stored in the first registers to the data stored in the second registers; and

third registers to store the results of the XOR logic;

search logic configured to identify addresses of that NAND memory array where the results stored in the third registers indicates a match between the data read from that NAND memory array and the user pattern; and

address registers to store the identified addresses; and

a processor coupled to each NAND memory array of the plurality of NAND memory arrays, the processor configured to load the user pattern and initiate a search of each NAND memory array of the plurality of NAND memory arrays in parallel.

11. The memory of claim 10 , further comprising:

at least one user parameter register to store a size of the user pattern, an accuracy setting for identifying matches, and a number of matches to be identified.

12. The memory of claim 10 , wherein the search logic receives an accuracy setting for identifying matches and identifies addresses of that NAND memory array where the results stored in the third registers indicate a match within the accuracy setting.

13. The memory of claim 10 , wherein the search logic is configured to identify addresses for matches from the results stored in the third registers for a previous page of data read from the NAND memory array concurrently with the first registers being loaded with a next page of data read from the NAND memory array.

14. The memory of claim 10 , wherein the processor is coupled to the plurality of NAND memory arrays through a single channel.

15. The memory of claim 10 , wherein the processor is coupled to each NAND memory array of the plurality of NAND memory arrays through a separate channel.

16. A method for performing a search within a memory, the method comprising:

reading a page of data from a memory array;

storing the page of data in first registers of a page buffer;

storing a user pattern in second registers of the page buffer;

comparing the data stored in the first registers to the user pattern stored in the second registers; and

storing, in address registers, concurrently with reading a following page of data from the memory array, addresses of the memory array where the comparison indicates a match between the data stored in the first registers and the user pattern stored in the second registers.

17. The method of claim 16 , wherein comparing the data stored in the first registers to the user pattern stored in the second registers comprises XORing the data stored in the first registers to the user pattern stored in the second registers.

18. The method of claim 16 , further comprising:

setting a match accuracy,

wherein storing addresses of the memory array comprises storing addresses of the memory array where the comparison indicates a match within the match accuracy.

19. The method of claim 16 , further comprising:

setting a number of matches,

wherein storing addresses of the memory array comprises storing addresses until the number of matches is reached.

20. The method of claim 16 , further comprising:

setting a size of the user pattern;

wherein storing the user pattern in the second registers comprises storing multiple copies of the user pattern in the second registers based on the size of the user pattern.

21. The method of claim 16 , further comprising:

outputting the addresses stored in the address registers to an input/output interface once the search is complete.