Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V TH ) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V TH1 ) of the memory cell and determining whether the V TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V TH2 ); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V TH1 and the V TH2 .
1. An apparatus comprising:
a memory array comprising a memory cell;
a memory controller coupled to the memory array and configured to:
determine that a first electrical response is within an overlapped electrical response region; and
determine a second electrical response of the memory cell;
a ramp generator coupled to the memory controller, wherein the ramp generator is configured to ramp a bias on the memory cell after the determination that the first electrical response is within the overlapped electrical response region; and
a comparator configured to determine a state of the memory cell based at least in part on a comparison between the first electrical response and the second electrical response.
2. The apparatus of claim 1 , further comprising:
a write circuit coupled to the memory cell, wherein the write circuit is configured to apply a write pulse to the memory cell based at least in part on ramping the bias.
3. The apparatus of claim 1 , further comprising:
a first hold circuit coupled to the comparator, wherein the first hold circuit is configured to store the first electrical response prior to the comparison between the first electrical response and the second electrical response.
4. The apparatus of claim 1 , further comprising:
a second hold circuit coupled to the comparator, wherein the second hold circuit is configured to store the second electrical response prior to the comparison between the first electrical response and the second electrical response.
5. The apparatus of claim 1 , wherein the memory cell is in the overlapped electrical response region between a first state distribution and a second state distribution.
6. The apparatus of claim 5 , wherein the first state distribution corresponds to a first logic state and the second state distribution corresponds to a second logic state.
7. The apparatus of claim 1 , wherein the memory cell comprises a phase change memory cell.
8. A method comprising:
determining that a first electrical response of a memory cell is within an overlapped electrical response region;
applying a bias to the memory cell after determining that the first electrical response of the memory cell is within the overlapped electrical response region;
determining a second electrical response of the memory cell after determining that the first electrical response of the memory cell is within the overlapped electrical response region; and
determining a state of the memory cell based at least in part on a comparison between the first electrical response within the overlapped electrical response region and the second electrical response.
9. The method of claim 8 , further comprising:
ramping a bias on the memory cell based at least in part on applying the bias to the memory cell.
10. The method of claim 9 , further comprising:
applying a write pulse to the memory cell based at least in part on ramping the bias.
11. The method of claim 8 , further comprising:
storing, in a first circuit, the first electrical response prior to the comparison between the first electrical response and the second electrical response.
12. The method of claim 8 , further comprising:
storing, in a second circuit, the second electrical response prior to the comparison between the first electrical response and the second electrical response.
13. The method of claim 8 , further comprising:
determining that the memory cell is in the overlapped electrical response region between a first state distribution and a second state distribution.
14. A method comprising:
determining that a first electrical response of a memory cell is within an overlapped electrical response region;
applying a bias to the memory cell after determining that the first electrical response of the memory cell is within the overlapped electrical response region;
determining a second electrical response of the memory cell based at least in part on the determination that the first electrical response of the memory cell is within the overlapped electrical response region; and
reading the memory cell based at least in part on determining the second electrical response.
15. The method of claim 14 , further comprising:
comparing the first electrical response and the second electrical response based at least in part on determining the second electrical response.
16. The method of claim 15 , wherein comparing the first electrical response and the second electrical response comprises:
determining that a voltage of the second electrical response is greater than a voltage of the first electrical response.
17. The method of claim 16 , wherein reading the memory cell comprises:
determining that the memory cell is in a set state based at least in part on determining that the voltage of the second electrical response is greater than the voltage of the first electrical response.
18. The method of claim 15 , wherein comparing the first electrical response and the second electrical response comprises:
determining that a voltage of the second electrical response is less than a voltage of the first electrical response.
19. The method of claim 18 , wherein reading the memory cell comprises:
determining that the memory cell is in a reset state based at least in part on determining that the voltage of the second electrical response is less than the voltage of the first electrical response.