Frequency synthesis for memory input-output operations
View Patent ↗A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
1. A method of operating a memory device, the method comprising:
receiving, at a mode register coupled to a memory channel, a training frequency used to synthesize a clock signal;
receiving at the memory channel a command to enter a training mode; and
receiving, by the memory channel, a training pattern associated with the training mode used to match a phase of the synthesized clock signal.
2. The method of claim 1 , wherein the training frequency comprises a command/address (CA) training frequency and the training mode comprises a CA training mode, the method further comprising:
before the CA training frequency is received, powering up the memory channel in a low speed CA mode; and
after the CA training frequency is received, receiving, by the memory channel, the command to enter the CA training mode.
3. The method of claim 1 , further comprising synthesizing, by a clock circuit coupled to the memory channel, the clock signal during at least a portion of a training sequence associated with the training mode.
4. The method of claim 1 , further comprising generating, by a clock circuit coupled to the memory channel, the synthesized clock signal based on the received training frequency.
5. The method of claim 1 , further comprising matching, by at least one clock circuit, the phase of the synthesized clock signal to a phase provided by the training pattern,
wherein the training pattern includes encoded timing data.
6. The method of claim 1 , further comprising providing, by the mode register and to at least one clock circuit coupled to the memory channel, the training frequency to set a frequency of the clock signal to be synthesized by the at least one clock circuit.
7. The method of claim 1 , further comprising
setting a frequency of the synthesized clock signal to be the training frequency received from the mode register; and
matching, by at least one clock circuit coupled to the mode register, the phase of the synthesized clock signal to a phase provided by the training pattern.
8. The method of claim 7 , wherein the training pattern is provided to the memory channel until the frequency of the synthesized clock signal is locked by the at least one clock circuit.
9. The method of claim 7 , wherein the training pattern is provided to the memory channel until the phase and the frequency of the synthesized clock signal are locked by the at least one clock circuit.
10. The method of claim 1 , further comprising receiving, by a clock circuit coupled to the memory channel, a system clock signal,
wherein the synthesized clock signal is an internal clock signal based at least in part on the received system clock signal.
11. An apparatus, comprising:
a memory channel including a first circuit and a second circuit,
the first circuit configured to receive a commandladdress (CA) training frequency during a low speed CA mode of the memory channel, and synthesize a clock signal based on the CA training frequency,
the second circuit configured to receive a CA training pattern associated with the CA training mode used to match a phase of the synthesized clock signal to a phase of the CA training pattern.
12. The apparatus of claim 11 , wherein the memory channel is configured to, before the CA training pattern is received by the second circuit, receive a command to enter a CA training mode.
13. The apparatus of claim 12 , wherein the memory channel is configured to provide a signal to indicate the second circuit has locked the phase and the frequency of the synthesized clock signal.
14. The apparatus of claim 11 , wherein the synthesized clock signal is a synthesized internal clock signal.
15. The apparatus of claim 11 , wherein the memory channel is configured to receive the CA training pattern for a defined period of time.
16. The apparatus of claim 11 , wherein the memory channel is configured to receive the CA training pattern until the second circuit has locked the phase and the frequency of the synthesized clock signal.
17. A method of operating a memory device, the method comprising:
receiving, by a clock circuit coupled to a memory channel, an input/output (I/O) training frequency;
receiving, by at least one I/O lane in the memory channel, a write training pattern; and
driving, via the at least one IO lane, a read pattern after the write training pattern is received.
18. The method of claim 17 , further comprising, after the receiving of the I/O training frequency, generating, by the clock circuit, a synthesized clock signal.
19. The method of claim 18 , further comprising matching a phase of the synthesized clock signal to a phase provided by the received write training pattern.
20. The method of claim 17 , further comprising, prior to the receiving of the write training pattern, receiving, by the memory channel, a command to enter an I/O training mode.