Buses for pattern-recognition processors
Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.
1. A system, comprising:
a pattern-recognition processor, wherein the pattern-recognition processor comprises:
a plurality of memory elements and a detection cell coupled to the plurality of memory elements that when in operation search a data stream received by the pattern-recognition processor according to a search criterion;
a first input configured to receive a first signal, wherein the pattern-recognition processor is configured to process the first signal to perform a first function at the pattern-recognition processor; and
a second input configured to receive a second signal, wherein the pattern-recognition processor is configured to process the second signal to perform a second function at the pattern-recognition processor; and
a memory, wherein the memory comprises:
a third input configured to receive the first signal, wherein the memory is configured to process the first signal to perform the first function at the memory; and
a fourth input configured to receive the second signal, wherein the memory is configured to process the second signal to perform a third function at the memory.
2. The system of claim 1 , comprising a pattern-recognition bus controller coupled to the pattern-recognition processor, wherein the pattern-recognition bus controller is configured to transmit the first signal and the second signal to the pattern-recognition processor.
3. The system of claim 2 , comprising a memory bus controller coupled to the memory, wherein the memory bus controller is configured to transmit the first signal and the second signal to the memory.
4. The system of claim 3 , comprising a bus coupled to each of the pattern-recognition processor and the memory bus controller, wherein the pattern-recognition bus controller is configured to transmit the first signal and the second signal to the pattern-recognition processor via the bus, wherein the memory bus controller is configured to transmit the first signal and the second signal to the memory via the bus.
5. The system of claim 3 , comprising a pattern-recognition bus coupled to the pattern-recognition bus controller and the pattern-recognition processor, wherein the pattern-recognition bus controller is configured to transmit the first signal and the second signal to the pattern-recognition processor via the pattern-recognition bus.
6. The system of claim 3 , comprising a memory bus coupled to the memory bus controller and the memory, wherein the memory bus controller is configured to transmit the first signal and the second signal to the memory via the memory bus.
7. The system of claim 1 , wherein the pattern-recognition processor comprises a fifth input configured to receive a third signal, wherein the pattern-recognition processor is configured to process the third signal to perform a fourth function at the pattern-recognition processor when the pattern-recognition processor is in a first mode of operation.
8. The system of claim 7 , wherein the pattern-recognition processor is configured to process the third signal to perform a fifth function at the pattern-recognition processor when the pattern-recognition processor is in a second mode of operation.
9. The system of claim 8 , wherein the memory comprises a sixth input configured to receive the third signal, wherein the memory is configured to process the third signal to perform a sixth function at the memory.
10. The system of claim 1 , wherein the first input and the third input are configured to receive the first signal as a clock chip enable signal, a data strobe signal, or a data mask signal, wherein the second input and the fourth input are configured to receive the second signal as a row address strobe signal, a column address strobe signal, a write enable signal, or a burst chop signal.
11. A system, comprising:
a processing unit (PU) configured to generate a plurality of control signals;
a pattern-recognition processor coupled to the PU, wherein the pattern-recognition processor comprises a plurality of memory elements and a detection cell coupled to the plurality of memory elements that when in operation search a data stream received by the pattern-recognition processor according to a search criterion, wherein the pattern-recognition processor is configured to:
receive the plurality of control signals;
process a first control signal of the plurality of control signals to perform a first function at the pattern-recognition processor; and
process a second control signal of the plurality of control signals to perform a second function at the pattern-recognition processor; and
a memory coupled to the PU, wherein the memory is configured to:
receive the plurality of control signals;
process the first control signal of the plurality of control signals to perform the first function at the memory; and
process the second control signal of the plurality of control signals to perform a third function at the memory.
12. The system of claim 11 , wherein the PU is configured to generate a plurality of address signals and a plurality of data signals.
13. The system of claim 12 , wherein the memory is configured to receive the plurality of address signals and process the plurality of address signals to perform a fourth function at the memory.
14. The system of claim 13 , wherein the pattern-recognition processor is configured to receive the plurality of address signals and process the plurality of address signals to perform the fourth function at the pattern-recognition processor when the pattern-recognition processor is in a first mode.
15. The system of claim 14 , wherein the pattern-recognition processor is configured to receive the plurality of address signals and process the plurality of address signals to perform a fifth function at the pattern-recognition processor when the pattern-recognition processor is in a second mode.
16. The system of claim 12 , wherein the memory is configured to receive the plurality of data signals and process the plurality of data signals to perform a fourth function at the memory.
17. The system of claim 16 , wherein the pattern-recognition processor is configured to receive the plurality of data signals and process the plurality of data signals to perform the fourth function at the pattern-recognition processor when the pattern-recognition processor is in a first mode.
18. The system of claim 17 , wherein the pattern-recognition processor is configured to receive the plurality of data signals and process the plurality of data signals to perform a fifth function at the pattern-recognition processor when the pattern-recognition processor is in a second mode.
19. A method, comprising:
transmitting a first signal to a pattern-recognition processor that when in operation a searches a data stream according to a search criterion via a plurality of memory elements and a detection cell coupled to the plurality of memory elements;
transmitting the first signal to a memory;
transmitting a second signal to the pattern-recognition processor;
transmitting the second signal to the memory;
processing the first signal at the pattern-recognition processor to perform a first function at the pattern-recognition processor;
processing the second signal at the pattern-recognition processor to perform a second function at the pattern-recognition processor;
processing the first signal at the memory to perform the first function at the memory; and
processing the second signal at the memory to perform a third function at the memory.
20. The method of claim 19 , comprising:
changing a mode of operation of the pattern-recognition processor; and
transmitting a third signal from the pattern-recognition processor.