Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry
Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.
1. A method of forming an array, comprising:
forming rows of conductive vias over a substrate, the rows comprising a first series of the rows and a second series of the rows, individual of the conductive vias comprising first and second opposing upper end-walls; and
selectively depositing a conductive material onto:
the first upper end-walls of the individual conductive vias in the second series of the rows relative to the second upper end-walls of the individual conductive vias in the second series of the rows; and
the second upper end-walls of the individual conductive vias in the first series of the rows relative to the first upper end-walls of the individual conductive vias in the first series of the rows.
2. The method of claim 1 wherein the second upper end-walls of the individual conductive vias in the second series of the rows and the first upper end-walls of the individual conductive vias in the first series of the rows are masked during said selectively depositing whereby the conductive material is not deposited over said second upper end-walls of the individual conductive vias in the second series of the rows and whereby the conductive material is not deposited over said first upper end-walls of the individual conductive vias in the first series of the rows.
3. The method of claim 1 wherein the individual conductive vias comprise opposing sidewalls, at least some of the sidewalls being masked during said selectively depositing.
4. The method of claim 3 wherein only some of the sidewalls are masked during said selectively depositing, another some of the sidewalls being exposed at a start of said selectively depositing and the conductive material being selectively deposited onto the another some of the sidewalls that are exposed at the start of said selectively depositing.
5. The method of claim 1 wherein the conductive vias individually comprise a top, at least some of the top being exposed at a start of said selectively depositing and the conductive material being selectively deposited onto at least some of the top at the start of the selectively depositing.
6. The method of claim 5 wherein all of the top is exposed at the start of the selectively depositing and the conductive material being selectively deposited onto all of the top at the start of the selectively depositing.
7. The method of claim 1 wherein the first series of the rows individually alternate every-other-one with the second series of the rows.
8. The method of claim 1 comprising forming a plurality of capacitors individually comprising a lower conductive electrode, an upper conductive electrode, and a capacitor insulator there-between; individual of the lower conductive electrodes being electrically coupled to the selectively-deposited conductive material of the individual conductive vias.
9. The method of claim 8 comprising forming the array of capacitors and the conductive vias as a part of a memory circuitry.
10. The method of claim 9 wherein the memory circuitry comprises a DRAM comprising individual memory cells having a transistor and one of the plurality of capacitors.
11. A method of forming an array, comprising:
forming rows of conductive vias over a substrate, individual of the conductive vias comprising first and second opposing upper end-walls;
covering the first and second upper end-walls with a covering material;
masking a first series of the rows with a first mask on the substrate to leave a second series of the rows unmasked;
removing the covering material from and to expose the first upper end-walls in the unmasked second series of the rows while the first series of the rows is masked with the first mask;
after removing the covering material from and to expose the first upper end-walls in the unmasked second series of the rows, removing the first mask and masking the second series of the rows with a second mask on the substrate to leave the first series of the rows unmasked;
removing the covering material from and to expose the second upper end-walls in the unmasked first series of the rows while the second series of the rows is masked with the second mask;
after removing the covering material from and to expose the second upper end-walls in the unmasked first series of the rows, removing the second mask; and
after removing the first mask and the second mask and while the first and second series of the rows are exposed, selectively depositing a conductive material onto:
the exposed first upper end-walls of the individual conductive vias in the second series of the rows relative to the covering material that covers the second upper end-walls of the individual conductive vias in the second series of the rows; and
the exposed second upper end-walls of the individual conductive vias in the first series of the rows relative to the covering material that covers the first upper end-walls of the individual conductive vias in the first series of the rows.
12. The method of claim 11 wherein,
the removing of the covering material from and to expose the first upper end-walls in the unmasked second series of the rows comprises anisotropically directionally etching of the said covering material that is over said first upper end-walls at a first angle on a first side of perpendicular to a mean global outer horizontal surface of the substrate; and
the removing of the covering material from and to expose the second upper end-walls in the unmasked first series of the rows comprises anisotropically directionally etching of the said covering material that is over said second upper end-walls at a second angle from a second side opposite the first side of perpendicular to the mean global outer horizontal surface of the substrate.
13. The method of claim 12 wherein the first and second angles are of the same value but in different directions.
14. The method of claim 11 comprising forming the individual conductive vias to comprise a top, the conductive material being selectively deposited onto the top at a start of said first-stated selectively depositing of the conductive material.
15. The method of claim 11 comprising forming the individual conductive vias to have a top and covering the top with the covering material, the covering material covering the top being removed during the removing of the covering material from the first upper end-walls in the unmasked second series of the rows and exposing the top, the conductive material being selectively deposited onto the top at a start of said first-stated selectively depositing of the conductive material.
16. The method of claim 11 wherein the covering material is 100% sacrificial.
17. The method of claim 11 wherein the covering material is not 100% sacrificial.
18. The method of claim 11 wherein the covering material is conductive.
19. The method of claim 18 wherein the covering material is 100% sacrificial.
20. The method of claim 11 wherein the covering material is insulative.
21. The method of claim 11 wherein the covering material comprises polysilicon.
22. A method used in the fabrication of integrated circuitry, comprising:
forming an array of conductive vias in a first 2D horizontal lattice configuration, the array comprising a first series of rows of individual of the conductive vias and a second series of rows of the individual conductive vias, the individual vias comprising first and second opposing upper end-walls;
selectively depositing a conductive material onto:
the first upper end-walls of the individual conductive vias in the second series of rows relative to the second upper end-walls of the individual vias in the second series of rows; and
the second upper end-walls of the individual conductive vias in the first series of rows relative to the first upper end-walls of the individual conductive vias in the first series of rows; and
the selectively depositing forming a second 2D horizontal lattice configuration of the conductive material that is different from that of the first 2D horizontal lattice configuration.
23. The method of claim 22 wherein the first and second 2D horizontal lattice configurations are individually different ones of oblique, rectangular, square, centered rectangular, and hexagonal.
24. The method of claim 22 wherein the first 2D lattice configuration is one of rectangular or square and the second 2D lattice configuration is hexagonal.
25. The method of claim 22 wherein the first and second 2D horizontal lattice configurations are individually a Bravais lattice.
26. The method of claim 22 wherein the first and second 2D horizontal lattice configurations are individually not a Bravais lattice.