Techniques for read operations
Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
1. A method, comprising:
biasing a first gate of a first transistor to a first voltage;
precharging a first node to a second voltage based at least in part on biasing the first gate of the first transistor to the first voltage, the second voltage being based at least in part on the first voltage and on a first threshold voltage of the first transistor;
coupling a memory cell with the first node precharged to the second voltage based at least in part on precharging the first node;
biasing a second gate of a second transistor to a third voltage based at least in part on coupling the memory cell with the first node; and
applying a fourth voltage to a second node coupled with a latch and the second transistor based at least in part on applying the third voltage to the second gate of the second transistor, the fourth voltage being based at least in part on the third voltage and a second threshold voltage of the second transistor.
2. The method of claim 1 , further comprising:
determining a logic state stored on the memory cell based at least in part on applying the fourth voltage to the second node coupled with the latch.
3. The method of claim 1 , further comprising:
activating a third transistor to couple the first transistor with the first node, wherein precharging the first node is based at least in part on activating the third transistor; and
activating a fourth transistor, after activating the third transistor, to couple the first node with the second gate of the second transistor, wherein biasing the second gate of the second transistor is based at least in part on activating the fourth transistor.
4. The method of claim 1 , wherein:
the first transistor is associated with a reference voltage supplied to the latch during a read operation of the memory cell; and
the second transistor is associated with the fourth voltage indicating a logic state stored in the memory cell and supplied to the second node of the latch during the read operation of the memory cell.
5. The method of claim 1 , further comprising:
biasing the second gate of the second transistor to the first voltage before biasing the second gate to the third voltage; and
precharging a third node to a fifth voltage based at least in part on biasing the second gate of the second transistor to the first voltage, wherein the fifth voltage is based at least in part on the first voltage and on the second threshold voltage of the second transistor.
6. The method of claim 5 , further comprising, before applying the forth voltage to the second node:
applying a sixth voltage to a first capacitor coupled with the first node after precharging the first node, wherein the sixth voltage causes the third voltage applied to the second gate of the second transistor to increase to a seventh voltage; and
applying an eighth voltage to a second capacitor coupled with the third node after precharging the third node, wherein the eighth voltage causes the fifth voltage applied to the first gate of the first transistor to increase to a ninth voltage.
7. The method of claim 6 , further comprising:
applying a tenth voltage to a fourth node coupled with the latch, wherein the tenth voltage is based at least in part on the ninth voltage and the first threshold voltage of the first transistor;
comparing the fourth voltage applied to the second node coupled with the latch to the tenth voltage applied to the fourth node coupled with the latch; and
determining a logic state stored on the memory cell based at least in part on comparing the fourth voltage with the tenth voltage, wherein the fourth voltage is based at least in part on the seventh voltage and the second threshold voltage of the second transistor.
8. The method of claim 5 , further comprising:
activating a fifth transistor to couple the second transistor to the third node, wherein precharging the third node is based at least in part on activating the fifth transistor; and
activating a sixth transistor, subsequent to activating the fifth transistor, to couple the third node to the first gate of the first transistor, wherein biasing the first gate of the first transistor is based at least in part on activating the sixth transistor.
9. The method of claim 1 , wherein the first transistor and the second transistor each comprise a source follower circuit.