IP Library Granted Patent US 10,719,271
Granted Patent B2
US 10,719,271 · App. 16/193,126 · Granted Jul 21, 2020

Temperature correction in memory sub-systems

Inventors: Gianni Stephen Alsasua (Rancho Cordova, CA); Karl D. Schuh (Santa Cruz, CA); Ashutosh Malshe (Fremont, CA); Kishore Kumar Muchherla (Fremont, CA); Vamsi Pavan Rayaprolu (San Jose, CA); Sampath Ratnam (Boise, ID); Harish Reddy Singidi (Fremont, CA); Renato Padilla, Jr. (Folsom, CA)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F12/1009G11C16/26G11C16/3404G06F2212/1008G06F2212/657G11C16/0483
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Quick Facts
Patent No.
US 10,719,271
App. No.
16/193,126
Granted
Jul 21, 2020
Kind
B2
Abstract

Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

Claims (67)

1. A system, comprising:

a memory component comprising a plurality of physical addresses;

a processing device operably coupled to the memory component, the processing device configured to perform operations comprising:

receiving a write request describing a logical address;

receiving a temperature signal from a temperature sensor associated with a memory device;

determining a write temperature code based at least in part on the temperature signal;

generating a table entry for the logical address, the table entry comprising the write temperature code and a physical address corresponding to the logical address;

writing the table entry for the logical address to a table;

receiving a read request describing the logical address;

determining, based on the table entry and the logical address, the physical address;

determining a corrected threshold voltage for reading the physical address based at least in part on the write temperature code; and

reading the physical address using the corrected threshold voltage.

2. The system of claim 1 , wherein the determining of the write temperature code comprises classifying the temperature signal into one of a plurality of temperature ranges, wherein each temperature range of the plurality of temperature ranges corresponds to a temperature code value.

3. The system of claim 1 , wherein the processing device is further programmed to perform operations comprising, before determining the corrected threshold voltage, determining that the write temperature code differs from a nominal temperature code.

4. The system of claim 3 , wherein the determining of the corrected threshold voltage is also based at least in part on the nominal temperature code.

5. The system of claim 1 , wherein the processing device is further programmed to perform operations comprising:

receiving a read temperature signal from the temperature sensor associated with the memory device;

comparing the write temperature code to the read temperature signal;

selecting a corrected threshold voltage offset based at least in part on the comparing of the write temperature code to the read temperature signal; and

applying the corrected threshold voltage offset to a nominal threshold voltage to generate the corrected threshold voltage.

6. The system of claim 5 , wherein the processing device is further programmed to perform operations comprising determining a read temperature code based at least in part on the read temperature signal wherein the comparing of the write temperature code to the read temperature signal comprises comparing the write temperature code to the read temperature code.

7. The system of claim 1 , wherein the processing device is further programmed to perform operations comprising:

before determining the corrected threshold voltage, reading the physical address using a nominal threshold voltage; and

executing an error recovery routine wherein the reading of the physical address using the corrected threshold voltage is a first remedial action of the error recovery routine.

8. A method, comprising:

receiving a write request describing a logical address at a memory device;

receiving a temperature signal from a temperature sensor associated with the memory device;

determining a write temperature code based at least in part on the temperature signal;

generating a table entry for the logical address, the table entry comprising the write temperature code and a physical address corresponding to the logical address;

writing the table entry for the logical address to a table;

receiving a read request describing the logical address;

determining, based on the table entry and the logical address, the physical address;

determining a corrected threshold voltage for reading the physical address based at least in part on the write temperature code; and

reading the physical address using the corrected threshold voltage.

9. The method of claim 8 , wherein the determining of the write temperature code comprises classifying the temperature signal into one of a plurality of temperature ranges, wherein each temperature range of the plurality of temperature ranges corresponds to a temperature code value.

10. The method of claim 8 , further comprising, before determining the corrected threshold voltage, determining that the write temperature code differs from a nominal temperature code.

11. The method of claim 10 , wherein the determining of the corrected threshold voltage is also based at least in part on the nominal temperature code.

12. The method of claim 8 , further comprising:

receiving a read temperature signal from the temperature sensor associated with the memory device;

comparing the write temperature code to the read temperature signal;

selecting a corrected threshold voltage offset based at least in part on the comparing of the write temperature code to the read temperature signal; and

applying the corrected threshold voltage offset to a nominal threshold voltage to generate the corrected threshold voltage.

13. The method of claim 12 , further comprising determining a read temperature code based at least in part on the read temperature signal, wherein the comparing of the write temperature code to the read temperature signal comprises comparing the write temperature code to the read temperature code.

14. The method of claim 8 , further comprising:

before determining the corrected threshold voltage, reading the physical address using a nominal threshold voltage; and

executing an error recovery routine wherein the reading of the physical address using the corrected threshold voltage is a first remedial action of the error recovery routine.

15. A non-transitory machine-readable storage medium comprising instructions thereon that, when executed by a processing device, cause the processing device to perform operations comprising:

receiving a write request describing a logical address at a memory device;

receiving a temperature signal from a temperature sensor associated with the memory device;

determining a write temperature code based at least in part on the temperature signal;

generating a table entry for the logical address, the table entry comprising the write temperature code and a physical address corresponding to the logical address;

writing the table entry for the logical address to a table;

receiving a read request describing the logical address;

determining, based on the table entry and the logical address, the physical address;

determining a corrected threshold voltage for reading the physical address based at least in part on the write temperature code; and

reading the physical address using the corrected threshold voltage.

16. The non-transitory machine-readable storage medium of claim 15 , wherein the determining of the write temperature code comprises classifying the temperature signal into one of a plurality of temperature ranges, wherein each temperature range of the plurality of temperature ranges corresponds to a temperature code value.

17. The non-transitory machine-readable storage medium of claim 15 , further comprising instructions thereon that, when executed by the processing device, cause the processing device to perform operations comprising, before determining the corrected threshold voltage, determining that the write temperature code differs from a nominal temperature code.

18. The non-transitory machine-readable storage medium of claim 17 , wherein the determining of the corrected threshold voltage is also based at least in part on the nominal temperature code.

19. The non-transitory machine-readable storage medium of claim 15 , wherein the operations further comprise:

receiving a read temperature signal from the temperature sensor associated with the memory device;

comparing the write temperature code to the read temperature signal;

selecting a corrected threshold voltage offset based at least in part on the comparing of the write temperature code to the read temperature signal; and

applying the corrected threshold voltage offset to a nominal threshold voltage to generate the corrected threshold voltage.

20. The non-transitory machine-readable storage medium of claim 19 , wherein:

the operations further comprise determining a read temperature code based at least in part on the read temperature signal; and

the comparing of the write temperature code to the read temperature signal comprises comparing the write temperature code to the read temperature code.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2019
From: ALSASUA, GIANNI STEPHEN; SCHUH, KARL D; MALSHE, ASHUTOSH; MUCHHERLA, KISHORE KUMAR; RAYAPROLU, VAMSI PAVAN; RATNAM, SAMPATH; SINGIDI, HARISH REDDY; PADILLA, RENATO, JR
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050687/0795 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Continuity (1)
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