IP Library Granted Patent US 10,795,746
Granted Patent B2
US 10,795,746 · App. 16/219,292 · Granted Oct 6, 2020

Automated power down based on state of firmware

Inventors: Jonathan Parry (Boise, ID); Nadav Grosz (Broomfield, CO)
Assignee: Micron Technology, Inc.
G06F11/0757G06F1/3225G06F1/3228G06F1/3237G06F1/3287G06F9/445G06F11/076G06F2201/81
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,795,746
App. No.
16/219,292
Granted
Oct 6, 2020
Kind
B2
Abstract

Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

Claims (35)

1. A memory device, comprising:

a memory array;

a firmware activity tracker; and

a memory controller, wherein the memory controller is programmed to perform operations comprising:

receiving one or more loading inputs from the firmware activity tracker indicating that a first instance of firmware has either not been successfully loaded, or has loaded but is not valid and operable;

after receiving the one or more loading inputs, receiving one or more reloading status inputs from the firmware activity tracker indicating a number of unsuccessful attempts to load the firmware; and

if the one or more reloading status inputs indicates that the number of unsuccessful attempts has reached a programmable threshold, entering the memory device into a reduced-power state.

2. The memory device of claim 1 , wherein entering the memory device into a reduced-power state includes stopping a clock of the memory device.

3. The memory device of claim 1 , wherein entering the memory device into a reduced-power state includes throttling a clock of the memory device.

4. The memory device of claim 1 , wherein entering the memory device into a reduced-power state includes entering the memory device into a protected state.

5. The memory device of claim 1 , wherein entering the memory device into a reduced-power state includes gating off power to selected power domains of the memory device.

6. The memory device of claim 1 , wherein entering the memory device into a reduced-power state includes using voltage control for the memory device.

7. The memory device of claim 1 , wherein the firmware activity tracker includes a portion of a read-only memory (ROM).

8. The memory device of claim 1 , wherein the firmware activity tracker comprises a counter configured to track the number of unsuccessful attempts to load the firmware.

9. The memory device of claim 1 , wherein the one or more reloading status inputs from the firmware activity tracker indicate an elapsed time for unsuccessful attempts to load the firmware, wherein if the one or more reloading status inputs indicates that the elapsed time has reached a timeout threshold, the memory device is entered into the reduced-power state.

10. The memory device of claim 9 , wherein the firmware activity tracker comprises a timer configured to track the elapsed time for unsuccessful attempts to load the firmware.

11. A memory device, comprising:

a memory array;

a firmware activity tracker; and

a memory controller, wherein the memory controller is programmed to perform operations comprising:

receiving one or more loading inputs from the firmware activity tracker indicating that a first instance of firmware has either not been successfully loaded, or has loaded but is not valid and operable;

after receiving the one or more loading inputs, receiving one or more reloading status inputs from the firmware activity tracker indicating an elapsed time for unsuccessful attempts to load the firmware; and

if the one or more reloading status inputs indicates that the elapsed time has reached a timeout threshold, entering the memory device into a reduced-power state.

12. The memory device of claim 11 , wherein entering the memory device into a reduced-power state includes stopping a clock of the memory device.

13. The memory device of claim 11 , wherein entering the memory device into a reduced-power state includes throttling a clock of the memory device.

14. The memory device of claim 11 , wherein the memory controller is programmed using a bootstrap program.

15. The memory device of claim 11 , wherein the firmware activity tracker comprises a timer configured to track the elapsed time for unsuccessful attempts to load the firmware.

16. A non-transitory computer readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:

receiving a one or more loading inputs from a firmware activity tracker indicating that a first instance of firmware has either not been successfully loaded, or has loaded but is not valid and operable;

after receiving the one or more loading inputs, receiving one or more reloading status inputs from the firmware activity tracker indicating a number of unsuccessful attempts to load the firmware; and

if the one or more reloading status inputs indicates that the number of unsuccessful attempts has reached a programmable threshold, entering the memory device into a reduced-power state.

17. The non-transitory computer readable storage medium of claim 16 , wherein the firmware activity tracker includes a portion of a read-only memory (ROM).

18. The non-transitory computer readable storage medium of claim 16 , wherein the firmware activity tracker comprises a counter configured to track the number of unsuccessful attempts to load the firmware.

19. The non-transitory computer readable storage medium of claim 16 , wherein entering the memory device into a reduced-power state includes gating off power to selected power domains of the memory device.

20. The non-transitory computer readable storage medium of claim 16 , wherein entering the memory device into a reduced-power state includes using voltage control for the memory device.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2019
From: PARRY, JONATHAN; GROSZ, NADAV
To: MICRON TECHNOLOGY, INC.
Reel/Frame 049348/0505 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Continuity (1)
Related Publication 20200192740A1 · Jun 18, 2020