Dual speed memory

1. An apparatus, comprising:

a first number of memory devices coupled to a host via a first number of ports; and

a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein the first number of memory devices are configured to transfer a first portion of data between the first number of memory devices and the host at a first clock speed via the first number of ports in response to receiving a first number of commands from the host and the second number of memory devices are configured to transfer a second portion of data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports in response to receiving a second number of commands from the host to transfer data between the first and second number of memory devices, and wherein the first portion of data is transferred between the first number of memory devices and the host while the second portion of data is transferred between the first number of memory devices and the second number of memory devices.

2. The apparatus of claim 1 , wherein the second clock speed is twice as fast as the first clock speed.

3. The apparatus of claim 1 , wherein the first number of memory devices are configured to execute the first number of commands by sending a status signal from a controller coupled to the first and second number of memory device to the host.

4. The apparatus of claim 1 , wherein the first number of memory devices are configured to receive the first number of commands from the host in response to a change in a ready/wait signal sent from a controller coupled to the first and second number of memory device to the host.

5. The apparatus of claim 1 , wherein the apparatus is a non-volatile dual in-line memory module (NVDIMM), the first number of memory devices are volatile memory devices, and the second number of memory device are non-volatile memory devices.

6. An apparatus, comprising:

a register clock driver (RCD);

a controller coupled to the RCD and configured to receive commands from a host via the RCD;

a first number of memory devices coupled to the controller; and

a second number of memory devices that each comprise a first data port that is couplable to the host and a second data port coupled to the controller, wherein the controller is configured execute a first number of commands received from the host to transfer a first portion data between the second number of memory devices and the host at a first clock speed and execute a second number of commands received from the host to transfer a second portion of data between the first number of memory devices and the second number of memory devices at a second clock speed, and wherein the first portion of data is transferred between the second number of memory devices and the host while the second portion of data is transferred between the first number of memory devices and the second number of memory devices.

7. The apparatus of claim 6 , wherein the first clock speed is 4 giga-transfers per second and the second clock speed is 8 giga-transfers per second.

8. The apparatus of claim 6 , wherein the first number of commands to transfer data between the second number of memory devices and the host are performed without latency based on a difference between the first clock speed and the second clock speed.

9. The apparatus of claim 6 , wherein a ratio between the second clock speed and the first clock speed is 2:1.

10. The apparatus of claim 6 , wherein a ratio between the second clock speed and the first clock speed is 3:1.

11. The apparatus of claim 6 , wherein the controller is coupled to the first number of memory devices via a first interface.

12. The apparatus of claim 6 , wherein the controller is coupled to the second number of memory devices via a second interface and wherein the second interface is couplable to the host.

13. A method, comprising:

transferring, in response to receiving a first command from a host, data from a first memory die of a pair of memory dies via a first port, wherein the pair of memory dies are coupled to one another and the host via the first port and wherein the data is transferred from the first memory die at a first clock speed; and

transferring, in response to receiving a second command from the host, the data from a second memory die of the pair of memory dies via a second port, wherein the pair of memory dies are coupled to one another and a controller via the second port and wherein the data is transferred from the second memory die at a second clock speed.

14. The method of claim 13 , further comprising isolating the second memory die from the host via the first port.

15. The method of claim 13 , further comprising isolating the first memory die from the controller via the second port.

16. The method of claim 13 , further comprising receiving the first command and the second command during a same clock cycle.

17. The method of claim 13 , further comprising transferring the data from the first memory die to the second memory die in response to the first command, wherein the second command comprises receiving the transferred data at the second memory die.

18. The method of claim 17 , further comprising transferring the data from the second memory die during a clock cycle that follows transferring the data from the first memory die based on the first memory device executing the first command at the first clock speed.

19. The method of claim 17 , further comprising transferring the data from the second memory die during a clock cycle that immediately follows transferring the data from the first memory die based on the first memory device executing the first command at the first clock speed.