Phase lock circuitry using frequency detection
A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.
1. An apparatus comprising:
a phase-locked loop (PLL) circuit configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, wherein the PLL circuit comprises a frequency detector configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, wherein, prior to detection of the frequency deviation, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal such that the one of the reference clock signal or the feedback clock signal is delayed relative to a non-delayed one of the reference clock signal or the feedback clock signal; and
a voltage-controlled oscillator circuit configured to provide the feedback clock signal based on a value of the bias voltage.
2. The apparatus of claim 1 , wherein the frequency detector comprises a delay circuit configured to apply the asynchronous delay to the reference clock signal.
3. The apparatus of claim 2 , wherein the delay circuit comprises two serially-coupled inverters configured to receive the reference clock signal.
4. The apparatus of claim 1 , wherein the frequency detector comprises a delay circuit configured to apply the asynchronous delay to the reference clock signal during a first time period and to apply the asynchronous delay to the feedback clock signal during a second time period.
5. The apparatus of claim 4 , wherein the delay circuit comprises:
a first multiplexer configured to selectively provide the reference clock signal or the reference clock signal after application of the asynchronous delay based on a value of a control signal; and
a second multiplexer configured to selectively provide the feedback clock signal or the feedback clock signal after application of the asynchronous delay based on the value of the control signal.
6. The apparatus of claim 5 , wherein, in response to the control signal having a first value, the first multiplexer is configured to provide the reference clock signal and the second multiplexer is configured to provide the feedback clock signal after application of the asynchronous delay, wherein, in response to the control signal having a second value, the first multiplexer is configured to provide the reference clock signal after application of the asynchronous delay and the second multiplexer is configured to provide the feedback clock signal.
7. The apparatus of claim 6 , wherein the control signal is configured to transition from the first value to the second value and from the second value to the first value after a predetermined number clock cycles.
8. The apparatus of claim 5 , wherein the delay circuit further comprises:
a first pair of serially-coupled inverters configured to apply the asynchronous delay to the reference clock signal; and
a second pair of serially-coupled inverters configured to apply the asynchronous delay to the feedback clock signal.
9. The apparatus of claim 1 , wherein the PLL circuit further comprises a phase detector configured to cause adjustment of the value of the bias voltage in response to detection of a phase difference between the reference clock signal and the feedback clock signal.
10. The apparatus of claim 1 , wherein the PLL circuit further comprises a loop filter/charge pump configured to adjust the value of the bias voltage in response to detection of a phase difference between the reference clock signal and the feedback clock signal by the frequency detector.
11. The apparatus of claim 1 , wherein the voltage-controlled oscillator circuit is a multi-stage, voltage-controlled oscillator circuit configured to provide a plurality of phase-shifted clock signal based on the value of the bias voltage.