Thin film transistors and related fabrication techniques
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
1. A method, comprising:
forming a first plurality of vias and a second plurality of vias through a top layer of a stack that comprises a first layer, a second layer, and a third layer;
forming, using the first plurality of vias, a first cavity at the second layer;
forming, in the first cavity and using the first plurality of vias, a gate electrode for a transistor, the gate electrode at the second layer;
forming, using the second plurality of vias, a second cavity at the first layer;
forming, in the second cavity and using the second plurality of vias, a second electrode for the transistor, the second electrode at the first layer;
forming, using a via that is common to the first plurality of vias and the second plurality of vias, a third electrode for the transistor, the third electrode extending through at least the third layer;
removing, using the via, a portion of the gate electrode to form a third cavity at the second layer; and
forming, using the via, oxide material in the third cavity at the second layer and in contact with the gate electrode.
2. The method of claim 1 , wherein forming the gate electrode for the transistor comprises:
forming a channel at the second layer that is aligned with the first plurality of vias;
forming an insulating material that conforms to the channel; and
filling the channel with an electrode material based at least in part on forming the insulating material.
3. The method of claim 1 , further comprising:
removing, using the via, a portion of the second electrode to form a fourth cavity at the first layer; and
forming, using the via, ohmic material in the fourth cavity at the first layer and in contact with the second electrode.
4. The method of claim 1 , wherein forming the third electrode for the transistor comprises:
forming, using the via, a hole through the stack to a layer of logic circuitry; and
filling the hole with an electrode material.
5. The method of claim 1 , further comprising:
forming, using the via, a fourth cavity that spans the first layer and the second layer; and
forming, using the via, semiconductor material in the fourth cavity that spans the first layer and the second layer.
6. The method of claim 5 , further comprising:
forming, using the via, an insulating material in contact with the semiconductor material.
7. The method of claim 1 , further comprising:
forming, using the via, a fourth cavity at the third layer; and
forming, using the via, ohmic material in the fourth cavity at the third layer and in contact with the third electrode.
8. The method of claim 1 , wherein forming the second electrode for the transistor comprises:
forming a channel at the first layer that is aligned with the second plurality of vias, wherein the second plurality of vias forms a second row of vias that intersects a first row of vias formed by the first plurality of vias;
filling the channel at the first layer with an electrode material; and
forming a plurality of dielectric plugs corresponding to the second plurality of vias, wherein the dielectric plugs extend through the electrode material in the channel at the first layer.
9. A method comprising:
forming a first plurality of vias and a second plurality of vias through a top layer of a stack that comprises a first layer, a second layer, and a third layer;
forming, using the first plurality of vias, a first cavity at the second layer;
forming, in the first cavity and using the first plurality of vias, a gate electrode for a transistor, the gate electrode at the second layer;
forming, using the second plurality of vias, a second cavity at the first layer;
forming, in the second cavity and using the second plurality of vias, a second electrode for the transistor, the second electrode at the first layer;
forming, using a via that is common to the first plurality of vias and the second plurality of vias, a third electrode for the transistor, the third electrode extending through at least the third layer;
forming, using the via, a third cavity that spans the first layer and the second layer; and
forming, using the via, semiconductor material in the third cavity that spans the first layer and the second layer.
10. The method of claim 9 , further comprising:
forming, using the via, an insulating material in contact with the semiconductor material.
11. The method of claim 9 , wherein forming the gate electrode for the transistor comprises:
forming a channel at the second layer that is aligned with the first plurality of vias;
forming an insulating material that conforms to the channel; and
filling the channel with an electrode material based at least in part on forming the insulating material.
12. The method of claim 9 , further comprising:
removing, using the via, a portion of the gate electrode to form a fourth cavity at the second layer; and
forming, using the via, oxide material in the fourth cavity at the second layer and in contact with the gate electrode.
13. The method of claim 12 , further comprising:
removing, using the via, a portion of the second electrode to form a fifth cavity at the first layer; and
forming, using the via, ohmic material in the fifth cavity at the first layer and in contact with the second electrode.
14. The method of claim 9 , further comprising:
forming, using the via, a fourth cavity at the third layer; and
forming, using the via, ohmic material in the fourth cavity at the third layer and in contact with the third electrode.
15. The method of claim 9 , wherein forming the third electrode for the transistor comprises:
forming, using the via, a hole through the stack to a layer of logic circuitry; and
filling the hole with an electrode material.
16. The method of claim 9 , wherein forming the second electrode for the transistor comprises:
forming a channel at the first layer that is aligned with the second plurality of vias, wherein the second plurality of vias forms a second row of vias that intersects a first row of vias formed by the first plurality of vias;
filling the channel at the first layer with an electrode material; and
forming a plurality of dielectric plugs corresponding to the second plurality of vias, wherein the dielectric plugs extend through the electrode material in the channel at the first layer.
17. A method comprising:
forming a first plurality of vias and a second plurality of vias through a top layer of a stack that comprises a first layer, a second layer, and a third layer;
forming, using the first plurality of vias, a first cavity at the second layer;
forming, in the first cavity and using the first plurality of vias, a gate electrode for a transistor, the gate electrode at the second layer;
forming, using the second plurality of vias, a second cavity at the first layer;
forming, in the second cavity and using the second plurality of vias, a second electrode for the transistor, the second electrode at the first layer;
forming, using a via that is common to the first plurality of vias and the second plurality of vias, a third electrode for the transistor, the third electrode extending through at least the third layer;
forming, using the via, a third cavity at the third layer; and
forming, using the via, ohmic material in the third cavity at the third layer and in contact with the third electrode.
18. The method of claim 17 , wherein forming the gate electrode for the transistor comprises:
forming a channel at the second layer that is aligned with the first plurality of vias;
forming an insulating material that conforms to the channel; and
filling the channel with an electrode material based at least in part on forming the insulating material.
19. The method of claim 17 , further comprising:
removing, using the via, a portion of the gate electrode to form a fourth cavity at the second layer; and
forming, using the via, oxide material in the fourth cavity at the second layer and in contact with the gate electrode.
20. The method of claim 19 , further comprising:
removing, using the via, a portion of the second electrode to form a fifth cavity at the first layer; and
forming, using the via, ohmic material in the fifth cavity at the first layer and in contact with the second electrode.
21. The method of claim 17 , further comprising:
forming, using the via, a fourth cavity that spans the first layer and the second layer; and
forming, using the via, semiconductor material in the fourth cavity that spans the first layer and the second layer.
22. The method of claim 21 , further comprising:
forming, using the via, an insulating material in contact with the semiconductor material.
23. The method of claim 17 , wherein forming the third electrode for the transistor comprises:
forming, using the via, a hole through the stack to a layer of logic circuitry; and
filling the hole with an electrode material.
24. The method of claim 17 , wherein forming the second electrode for the transistor comprises:
forming a channel at the first layer that is aligned with the second plurality of vias, wherein the second plurality of vias forms a second row of vias that intersects a first row of vias formed by the first plurality of vias;
filling the channel at the first layer with an electrode material; and
forming a plurality of dielectric plugs corresponding to the second plurality of vias, wherein the dielectric plugs extend through the electrode material in the channel at the first layer.
25. A method, comprising:
forming a first plurality of vias and a second plurality of vias through a top layer of a stack that comprises a first layer, a second layer, and a third layer;
forming, using the first plurality of vias, a first cavity at the second layer;
forming, in the first cavity and using the first plurality of vias, a gate electrode for a transistor, the gate electrode at the second layer;
forming, using the second plurality of vias, a second cavity at the first layer;
forming, in the second cavity and using the second plurality of vias, a second electrode for the transistor, the second electrode at the first layer, wherein forming the second electrode for the transistor comprises:
forming a channel at the first layer that is aligned with the second plurality of vias, wherein the second plurality of vias forms a second row of vias that intersects a first row of vias formed by the first plurality of vias;
filling the channel at the first layer with an electrode material; and
forming a plurality of dielectric plugs corresponding to the second plurality of vias, wherein the dielectric plugs extend through the electrode material in the channel at the first layer; and
forming, using a via that is common to the first plurality of vias and the second plurality of vias, a third electrode for the transistor, the third electrode extending through at least the third layer.
26. The method of claim 25 , wherein forming the gate electrode for the transistor comprises:
forming a second channel at the second layer that is aligned with the first plurality of vias;
forming an insulating material that conforms to the second channel; and
filling the second channel with a second electrode material based at least in part on forming the insulating material.
27. The method of claim 25 , further comprising:
removing, using the via, a portion of the gate electrode to form a third cavity at the second layer; and
forming, using the via, oxide material in the third cavity at the second layer and in contact with the gate electrode.
28. The method of claim 27 , further comprising:
removing, using the via, a portion of the second electrode to form a fourth cavity at the first layer; and
forming, using the via, ohmic material in the fourth cavity at the first layer and in contact with the second electrode.
29. The method of claim 25 , further comprising:
forming, using the via, a third cavity that spans the first layer and the second layer; and
forming, using the via, semiconductor material in the third cavity that spans the first layer and the second layer.
30. The method of claim 29 , further comprising:
forming, using the via, an insulating material in contact with the semiconductor material.
31. The method of claim 25 , further comprising:
forming, using the via, a third cavity at the third layer; and
forming, using the via, ohmic material in the third cavity at the third layer and in contact with the third electrode.
32. The method of claim 25 , wherein forming the third electrode for the transistor comprises:
forming, using the via, a hole through the stack to a layer of logic circuitry; and
filling the hole with a second electrode material.