IP Library Granted Patent US 10,818,760
Granted Patent B2
US 10,818,760 · App. 16/357,583 · Granted Oct 27, 2020

Memory cells having electrically conductive nanodots and apparatus having such memory cells

Inventor: Nirmal Ramaswamy (Boise, ID)
Assignee: Micron Technology, Inc.
H01L29/42332B82Y10/00H01L27/11521H01L27/11524H01L29/40114H01L29/7881H01L29/7883Y10S977/774Y10S977/943
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,818,760
App. No.
16/357,583
Granted
Oct 27, 2020
Kind
B2
Abstract

Memory cells having a plurality of electrically conductive nanodots between a charge storage material and a dielectric, and apparatus having such memory cells, may facilitate non-volatile storage of data. The electrically conductive nanodots may be in contact with a surface of either the charge storage material, or a barrier material between the electrically conductive nanodots and the charge storage material.

Claims (35)

1. A memory cell, comprising:

a first dielectric between a charge storage material and a semiconductor;

a plurality of electrically conductive nanodots between the charge storage material and a control gate; and

a second dielectric between the control gate and the plurality of electrically conductive nanodots;

wherein each electrically conductive nanodot of the plurality of electrically conductive nanodots is in contact with a surface of a particular material selected from a group consisting of the charge storage material and a barrier material between the plurality of electrically conductive nanodots and the charge storage material.

2. The memory cell of claim 1 , wherein the second dielectric is in contact with the particular material.

3. The memory cell of claim 1 , wherein the charge storage material comprises a electrically conductive charge storage material.

4. The memory cell of claim 3 , wherein the electrically conductive charge storage material comprises a conductively doped semiconductor material.

5. The memory cell of claim 1 , wherein the charge storage material comprises a silicon-containing material.

6. The memory cell of claim 5 , wherein the silicon-containing material comprises at least one material selected from the group consisting of monocrystalline silicon, amorphous silicon and polycrystalline silicon.

7. The memory cell of claim 1 , wherein the memory cell comprises the barrier material between the plurality of electrically conductive nanodots and the charge storage material, and wherein the barrier material is a material selected from a group consisting of an oxidized product of the charge storage material, a nitridized product of the charge storage material and a nitridized product of the oxidized product of the charge storage material.

8. The memory cell of claim 1 , wherein each electrically conductive nanodot of the plurality of electrically conductive nanodots is in contact with the second dielectric.

9. A memory cell, comprising:

a first dielectric between an electrically conductive charge storage material and a semiconductor;

a plurality of metal-containing nanodots between the electrically conductive charge storage material and a control gate;

a dielectric barrier in contact with each metal-containing nanodot of the plurality of metal-containing nanodots, and between the plurality of metal-containing nanodots and the electrically conductive charge storage material; and

a second dielectric in contact with the dielectric barrier, and between the control gate and the plurality of metal-containing nanodots.

10. The memory cell of claim 9 , wherein the electrically conductive charge storage material comprises a silicon-containing material selected from a group consisting of conductively doped monocrystalline silicon, conductively doped amorphous silicon and conductively doped polycrystalline silicon.

11. The memory cell of claim 9 , wherein the dielectric barrier comprises a silicon-containing dielectric material selected from a group consisting of a silicon oxide, a silicon nitride and a silicon oxynitride.

12. The memory cell of claim 9 , wherein the electrically conductive charge storage material comprises a silicon-containing material and wherein the dielectric barrier comprises nitridized silicon-containing material of the electrically conductive charge storage material.

13. The memory cell of claim 9 , wherein the plurality of metal-containing nanodots comprises nanodots comprising at least one metal-containing material selected from a group consisting of elemental metals, metal alloys, metal nitrides and metal silicides.

14. The memory cell of claim 13 , wherein the metals of the elemental metals, metal alloys, metal nitrides and metal silicides of the at least one metal-containing material are selected from a group consisting of titanium, tantalum, tungsten, ruthenium, rhodium, and platinum.

15. An apparatus, comprising:

an array of non-volatile memory cells; and

a controller configured to access the array of non-volatile memory cells;

wherein at least one memory cell of the array of non-volatile memory cells comprises:

a first dielectric between a charge storage material and a semiconductor;

a plurality of electrically conductive nanodots between the charge storage material and a control gate; and

a second dielectric between the control gate and the plurality of electrically conductive nanodots;

wherein each electrically conductive nanodot of the plurality of electrically conductive nanodots is in contact with a surface of a particular material selected from a group consisting of the charge storage material and a barrier material between the plurality of electrically conductive nanodots and the charge storage material.

16. The apparatus of claim 15 , wherein the at least one memory cell comprises the barrier material between the plurality of electrically conductive nanodots and the charge storage material, wherein each electrically conductive nanodot of the plurality of electrically conductive nanodots is in contact with a surface of the barrier material, and wherein the surface of the barrier material is further in contact with the second dielectric.

17. The apparatus of claim 16 , wherein the charge storage material is an electrically conductive charge storage material, and wherein the barrier material is a dielectric material.

18. The apparatus of claim 16 , wherein the barrier material is a material selected from a group consisting of an oxidized product of the charge storage material, a nitridized product of the charge storage material and a nitridized product of the oxidized product of the charge storage material.

19. The apparatus of claim 15 , wherein the plurality of electrically conductive nanodots comprises nanodots comprising at least one metal-containing material selected from a group consisting of elemental metals, metal alloys, metal nitrides and metal silicides.

20. The apparatus of claim 15 , wherein the charge storage material comprises an electrically conductive charge storage material.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →