Programming multiple-level memory cells with multiple-pass
One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes reprogramming the lower page data to the memory cells prior to programming higher page data to the memory cells in a second pass of the multiple-pass programming operation.
1. A method for programming multiple-level memory cells, the method comprising:
programming lower page data to memory cells in a first pass of a multiple-pass programming operation to program the memory cells to respective desired threshold voltages; and
reprogramming the lower page data to the memory cells to reprogram the memory cells back to the respective desired threshold voltages after the threshold voltages of the memory cells have shifted down due to a time interval after the first pass prior to programming higher page data to the memory cells in a second pass of the multiple-pass programming operation,
wherein programming the higher page data to the memory cells in the second pass comprises programming the higher page data to the memory cells in the second pass such that in response to power being restored after a power loss during the second pass, programming of the higher page data to the memory cells is reinstated.
2. The method of claim 1 , further comprising:
pre-reading the lower page programmed memory cells prior to the second pass using a first read level,
wherein reprogramming the lower page data to the memory cells prior to programming higher page data to the memory cells in the second pass of the multiple-pass programming operation is carried out in response to a number of fail bits of the pre-read lower page memory cells using the first read level exceeding a predetermined threshold.
3. The method of claim 1 , wherein programming the higher page data to the memory cells comprises programming upper page data and extra page data to the memory cells in the second pass.
4. A memory device comprising:
an array of multiple-level memory cells; and
a controller configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data to the memory cells in a first pass to program the memory cells to respective desired threshold voltages and reprogram the lower page data to the memory cells to reprogram the memory cells back to the respective desired threshold voltages after the threshold voltages of the memory cells have shifted down due to a time interval after the first pass and program higher page data to the memory cells in a second pass,
wherein the controller is configured to, in response to power being restored after a power loss during the second pass, reinstate programming of the higher page data to the memory cells.
5. The memory device of claim 4 , wherein the controller is configured to skip the reprogramming of the lower page data to the memory cells in the second pass in response to a threshold voltage of the lower page programmed memory cells being above a predetermined threshold voltage.
6. The memory device of claim 4 , wherein the controller is configured to program the multiple-level memory cells as triple level memory cells.
7. The memory device of claim 4 , wherein the controller is configured to program the multiple-level memory cells as quad level memory cells.