Variable read error code correction
Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
1. A controller for variable read error code correction (ECC), the controller comprising:
a hardware interface to receive bits from a read, the read of a type, the type being one of several types assigned to reads; and
an ECC component to:
set a low-density parity-check (LDPC) iteration maximum based on the type, wherein the LDPC iteration maximum is less than a total number of possible LDPC decodes;
perform LDPC iterations, on the bits from the read, up to the LDPC iteration maximum; and
signal a read failure, in response to the LDPC iterations reaching the LDPC iteration maximum, to:
provoke other error correction options on the bits to recover data; or
indicate that the data is lost.
2. The controller of claim 1 , wherein the hardware interface is configured to receive the bits from a second read, the second read of a second type from the several types; and wherein the ECC component is configured to:
set a second LDPC iteration maximum based on the second type;
perform second LDPC iterations up to the second LDPC iteration maximum; and
signal a read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum.
3. The controller of claim 2 , wherein the second type is a read-error type.
4. The controller of claim 2 , wherein the second LDPC iteration maximum is a multiple of the LDPC iteration maximum.
5. The controller of claim 2 , wherein the second read is a result of a read error handling operation following the read failure in response to the LDPC iterations reaching the LDPC iteration maximum.
6. The controller of claim 2 , wherein, to signal the read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum, the ECC component is configured to provoke a read trial operation.
7. The controller of claim 1 , wherein the type is a performance type.
8. The controller of claim 1 , wherein the hardware interface is configured to receive bits from a third read, the third read of the type; and wherein the ECC component is configured to:
set the LDPC iteration maximum based on the type;
perform fewer of the LDPC iterations than the LDPC iteration maximum; and
signal a read success in response to the LDPC iterations terminating prior to reaching the LDPC iteration maximum.
9. A method for variable read error code correction (ECC), the method comprising:
receiving bits from a read, the read of a type, the type being one of several types assigned to reads;
setting a low-density parity-check (LDPC) iteration maximum based on the type, wherein the LDPC iteration maximum is less than a total number of possible LDPC decodes;
performing LDPC iterations, on the bits from the read, up to the LDPC iteration maximum; and
signaling a read failure a read failure, in response to the LDPC iterations reaching the LDPC iteration maximum, to:
provoke other error correction options on the bits to recover data; or
indicate that the data is lost.
10. The method of claim 9 , comprising:
receiving the bits from a second read, the second read of a second type from the several types;
setting a second LDPC iteration maximum based on the second type;
performing second LDPC iterations up to the second LDPC iteration maximum; and
signaling a read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum.
11. The method of claim 10 , wherein the second type is a read-error type.
12. The method of claim 10 , wherein the second LDPC iteration maximum is a multiple of the LDPC iteration maximum.
13. The method of claim 10 , wherein the second read is a result of a read error handling operation following the read failure in response to the LDPC iterations reaching the LDPC iteration maximum.
14. The method of claim 10 , wherein signaling the read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum provokes a read trial operation.
15. The method of claim 9 , wherein the type is a performance type.
16. The method of claim 9 , comprising:
receiving bits from a third read, the third read of the type;
setting the LDPC iteration maximum based on the type;
performing fewer of the LDPC iterations than the LDPC iteration maximum; and
signaling a read success in response to the LDPC iterations terminating prior to reaching the LDPC iteration maximum.
17. A machine readable medium including instructions for variable read error code correction (ECC), the instruction, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
receiving bits from a read, the read of a type, the type being one of several types assigned to reads;
setting a low-density parity-check (LDPC) iteration maximum based on the type, wherein the LDPC iteration maximum is less than a total number of possible LDPC decodes;
performing LDPC iterations, on the bits from the read, up to the LDPC iteration maximum; and
signaling a read failure a read failure, in response to the LDPC iterations reaching the LDPC iteration maximum, to:
provoke other error correction options on the bits to recover data; or
indicate that the data is lost.
18. The machine readable medium of claim 17 , wherein the operations comprise:
receiving the bits from a second read, the second read of a second type from the several types;
setting a second LDPC iteration maximum based on the second type;
performing second LDPC iterations up to the second LDPC iteration maximum; and
signaling a read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum.
19. The machine readable medium of claim 18 , wherein the second type is a read-error type.
20. The machine readable medium of claim 18 , wherein the second LDPC iteration maximum is a multiple of the LDPC iteration maximum.
21. The machine readable medium of claim 18 , wherein the second read is a result of a read error handling operation following the read failure in response to the LDPC iterations reaching the LDPC iteration maximum.
22. The machine readable medium of claim 18 , wherein signaling the read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum provokes a read trial operation.
23. The machine readable medium of claim 17 , wherein the type is a performance type.
24. The machine readable medium of claim 17 , wherein the operations comprise:
receiving bits from a third read, the third read of the type;
setting the LDPC iteration maximum based on the type;
performing fewer of the LDPC iterations than the LDPC iteration maximum; and
signaling a read success in response to the LDPC iterations terminating prior to reaching the LDPC iteration maximum.