Memory for embedded applications

1. A memory device, comprising:

an array of memory cells having a first area and configured to operate at a first voltage, wherein the array of memory cells comprises an array of self-selecting memory cells, each self-selecting memory cell comprising a chalcogenide storage and selector element; and

circuitry having a second area that at least partially overlaps the first area, the circuitry configured to operate at a second voltage lower than the first voltage, wherein the array of memory cells and the circuitry are on a single substrate.

2. The memory device of claim 1 , further comprising:

decoder circuitry coupled with an access line of the array of memory cells and configured to decode memory addresses for the array of memory cells, wherein the decoder circuitry is configured to operate at the first voltage and the circuitry is configured to access the array of memory cells using the decoder circuitry.

3. The memory device of claim 2 , wherein the circuitry comprises microcontroller circuitry configured to perform logic operations based at least in part on accessing the array of memory cells.

4. The memory device of claim 2 , wherein the circuitry comprises cryptographic controller circuitry or memory controller circuitry.

5. The memory device of claim 1 , wherein the circuitry comprises SRAM circuitry or DRAM circuitry.

6. The memory device of claim 1 , wherein the circuitry overlays a third area of the substrate and the array of memory cells overlays a fourth area of the substrate, at least a first portion of the third area coinciding with the fourth area and at least a second portion of the third area extending beyond the fourth area.

7. The memory device of claim 1 , wherein the circuitry overlays a third area of the substrate and the array of memory cells overlays a fourth area of the substrate, the third area entirely within the fourth area.

8. A memory device, comprising:

an array of memory cells having a first area and configured to operate at a first voltage; and

circuitry having a second area that at least partially overlaps the first area, the circuitry configured to operate at a second voltage lower than the first voltage, wherein the array of memory cells and the circuitry are on a single substrate,

wherein the memory device comprises a first layer adjacent to the substrate and a second layer adjacent to the first layer, and wherein the array of memory cells is fabricated in the second layer and the circuitry is fabricated in the first layer.

9. A memory device, comprising:

an array of memory cells having a first area; and

decoder circuitry having a second area smaller than the first area, the decoder circuitry at least partially overlapping the first area and coupled with an access line of the array of memory cells, wherein the array of memory cells and the decoder circuitry are on a single substrate.

10. The memory device of claim 9 , wherein the decoder circuitry is fabricated in a first layer of the memory device and the array of memory cells is fabricated in a second layer of the memory device that is above the first layer.

11. The memory device of claim 10 , further comprising:

controller circuitry fabricated in the first layer and configured to access the array of memory cells using the decoder circuitry, wherein the array of memory cells overlaps at least a portion of the controller circuitry.

12. The memory device of claim 11 , wherein the decoder circuitry is configured to operate at a first voltage and the controller circuitry is configured to operate at a second voltage lower than the first voltage.

13. The memory device of claim 11 , wherein the decoder circuitry comprises logic gates having a first gate oxide material and the controller circuitry comprises logic gates having a second gate oxide material different than the first gate oxide material.

14. The memory device of claim 11 , wherein the decoder circuitry comprises logic gates having a first thickness of a first gate oxide material and the controller circuitry comprises logic gates having a second thickness of a second gate oxide material, the first thickness different than the second thickness.

15. The memory device of claim 10 , further comprising:

interconnect circuitry fabricated in the second layer and coupled with the array of memory cells and an input/output connector of the memory device.

16. The memory device of claim 9 , wherein the array of memory cells overlaps all of the decoder circuitry.

17. The memory device of claim 9 , wherein a first deck of the memory device comprises the array of memory cells and the decoder circuitry, further comprising:

a second deck of the memory device comprising a second array of memory cells that overlaps at least a portion of second decoder circuitry, the second deck and the first deck contained in a single package.

18. The memory device of claim 9 , wherein a first deck of the memory device comprises the array of memory cells and the decoder circuitry, further comprising:

a second deck of the memory device comprising a second array of memory cells, the second array of memory cells comprising PCM cells or DRAM cells, the second deck and the first deck contained in a single package.

19. A method, comprising:

fabricating, on a substrate, controller circuitry configured to operate at a first voltage; and

fabricating, on the substrate, an array of memory cells configured to operate at a second voltage higher than the first voltage, each memory cell comprising a chalcogenide storage and selector element, the array of memory cells at least partially overlapping the controller circuitry.

20. The method of claim 19 , wherein:

fabricating the controller circuitry comprises fabricating transistors in a device layer over the substrate during a first fabrication step; and

fabricating the array of memory cells comprises fabricating the array of memory cells in a metallization layer over the device layer during a second fabrication step.

21. The method of claim 20 , further comprising:

fabricating decoder circuitry in the device layer, the decoder circuitry configured to decode addresses for the array of memory cells and comprising MOS logic gates having a first gate oxide,

wherein the controller circuitry comprises MOS logic gates having a second gate oxide different than the first gate oxide.

22. The method of claim 21 , wherein the second gate oxide has a different thickness or a different material composition than the first gate oxide.

23. The method of claim 19 , wherein the array of memory cells overlaps a first portion of the controller circuitry and a second portion of the controller circuitry extends beyond the array of memory cells.

24. The method of claim 19 , wherein the array of memory cells overlaps all of the controller circuitry.