3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
1. A semiconductor package, comprising:
a first die;
a second die disposed over the first die; and
a coupled inductor including:
a magnetic core having a single through-substrate via (TSV) extending at least substantially through the first die and including a portion projecting from the first die and extending into an opening in the second die,
a primary winding disposed in the first die around the TSV, and
a secondary winding disposed in the second die around the TSV.
2. The semiconductor package of claim 1 , wherein the primary winding is configured to induce a change in a magnetic field in the TSV in response to a first changing current in the primary winding, and wherein the secondary winding is configured to have a second changing current induced therein in response to the change in the magnetic field in the TSV.
3. The semiconductor package of claim 1 , wherein the secondary winding is configured to induce a change in a magnetic field in the TSV in response to a first changing current in the secondary winding, and wherein the primary winding is configured to have a second changing current induced therein in response to the change in the magnetic field in the TSV.
4. The semiconductor package of claim 1 , wherein the TSV comprises a ferromagnetic material.
5. The semiconductor package of claim 1 , wherein the TSV comprises a ferrimagnetic material.
6. The semiconductor package of claim 1 , wherein the primary winding comprises a substantially helical conductor disposed coaxially around the TSV.
7. The semiconductor package of claim 1 , wherein the secondary winding comprises a substantially helical conductor disposed coaxially around the TSV.
8. The semiconductor package of claim 1 , wherein the primary winding comprises a different number of turns around the TSV than the secondary winding.
9. The semiconductor package of claim 1 , wherein the primary winding comprises a same number of turns around the TSV as the secondary winding.
10. The semiconductor package of claim 1 , wherein the primary and secondary windings are electrically isolated from each other and from the TSV.
11. The semiconductor package of claim 1 , wherein one of the primary and secondary windings is electrically connected to a power supply and another of the primary and secondary windings is electrically connected to a load.
12. The semiconductor package of claim 1 , wherein the secondary winding is disposed in the second die around the portion of the TSV projecting from the first die and extending into the opening in the second die.