Arbitration techniques for managed memory
Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.
1. A method, comprising:
enabling a first subset of multiple memory die of a NAND memory system;
starting an active timer for each of the memory die in the first subset; disabling a second subset of multiple memory die of the NAND memory system, the second subset including a first memory die;
starting an inactive timer for each die of the second subset of memory die of the NAND memory system;
receiving a first memory request for a first memory access operation at power management circuitry of the NAND memory system, the first memory access operation corresponding to a location within a first portion of the NAND memory system, the first portion including the first die, the first memory request comprising a read request or a write request;
determining that the first memory request is for an inactive die;
responsive to determining that the first memory request is for the inactive die, buffering the first memory request;
determining that an inactive timer for the first memory die has expired;
responsive to determining that the inactive timer for the first memory die has expired, determining that a second memory die has an active timer that is a longest pending active timer of all other memory die in the enabled subset;
responsive to determining that the second memory die has the longest pending active timer, deactivating the second memory die and activating the first memory die; and responsive to activating the first memory die:
retrieving the buffered first memory request;
splitting the first memory request into a plurality of component operations selected from a set of possible component operations based upon a type of the first memory request, the set of possible component operations comprising sense, program, transfer to NAND, transfer from NAND, and erase operations;
determining a first power load corresponding to performing a first component operation of the plurality of component operations;
determining whether a sum of the first power load and a current power consumption exceeds a budgeted power consumption for the first die; and
responsive to determining that the sum of the first power load and the current power consumption does not exceed the budgeted power consumption, executing the first component operation of the plurality of component operations.
2. The method of claim 1 , comprising:
determining a second power load corresponding to performing a second component operation of the plurality of component operations;
determining whether a sum of the second power load and the current power consumption exceeds the budgeted power consumption; and
responsive to determining that the sum of the second power load and the current power consumption exceeds the budgeted power consumption, buffering the second component operation of the plurality of component operations.
3. The method of claim 1 , wherein the budgeted power consumption is established for an individual memory device within the NAND memory system.
4. The method of claim 1 , wherein the budgeted power consumption is established for a channel of an individual memory device within the NAND memory system.
5. The method of claim 1 , wherein executing the first component operation of the plurality of component operations results in an increase of the current power consumption.
6. The method of claim 1 , wherein completion of the first component operation of the plurality of component operations results in a decrease in the current power consumption.
7. The method of claim 1 , wherein the current power consumption is maintained in a first register.
8. A NAND memory system comprising:
multiple memory die;
a memory controller coupled to the multiple memory die with one or more channels, the memory controller configured to receive multiple memory requests and service the memory requests using the multiple memory die within a power budget;
wherein the memory controller includes power management circuitry configured to perform operations comprising:
enabling a first subset of the multiple memory die of the NAND memory system;
starting an active timer for each of the memory die in the first subset;
disabling a second subset of multiple memory die of the NAND memory system, the second subset including a first memory die;
starting an inactive timer for each die of the second subset of memory die of the NAND memory system;
receiving a first memory request for a first memory access operation at the power management circuitry, the first memory access operation corresponding to a location within a first portion of the NAND memory system, the first portion including the first die, the first memory request comprising a read request or a write request;
determining that the first memory request is for an inactive die;
responsive to determining that the first memory request is for the inactive die, buffering the first memory request;
determining that an inactive timer for the first memory die has expired;
responsive to determining that the inactive timer for the first memory die has expired, determining that a second memory die has an active timer that is a longest pending active timer of all other memory die in the enabled subset;
responsive to determining that the second memory die has the longest pending active timer, deactivating the second memory die and activating the first memory die; and
responsive to activating the first memory die:
retrieving the buffered first memory request;
splitting the first memory request into a plurality of component operations selected from a set of possible component operations based upon a type of the first memory request, the set of possible component operations comprising sense, program, transfer to NAND, transfer from NAND, and erase operations;
determining a first power load corresponding to performing a first component operation of the plurality of component operations;
determining whether a sum of the first power load and a current power consumption exceeds a budgeted power consumption for the first die; and
responsive to determining that the sum of the first power load and the current power consumption does not exceed the budgeted power consumption, executing the first component operation of the plurality of component operations.
9. The memory system of claim 8 , wherein the operations further comprise:
determining a second power load corresponding to performing a second component operation of the plurality of component operations;
determining whether a sum of the second power load and the current power consumption exceeds the budgeted power consumption; and
responsive to determining that the sum of the second power load and the current power consumption exceeds the budgeted power consumption, buffering the second component operation of the plurality of component operations.
10. The memory system of claim 8 , wherein the budgeted power consumption is established for an individual memory die of the multiple memory die.
11. The memory system of claim 8 , wherein the budgeted power consumption is established for a channel of an individual memory die of the multiple memory die.
12. The memory system of claim 8 , wherein executing the first component operation of the plurality of component operations results in an increase in current power consumption.
13. The memory system of claim 8 , wherein completion of the first component operation of the plurality of component operations results in a decrease in current power consumption.
14. The memory system of claim 8 , wherein the current power consumption is maintained in a first register.
15. A non-transitory machine-readable medium including instructions for power management of a NAND memory system, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
enabling a first subset of multiple memory die of a NAND memory system;
starting an active timer for each of the memory die in the first subset;
disabling a second subset of multiple memory die of the NAND memory system, the second subset including a first memory die;
starting an inactive timer for each die of the second subset of memory die of the NAND memory system;
receiving a first memory request for a first memory access operation at power management circuitry of the NAND memory system, the first memory access operation corresponding to a location within a first portion of the memory system, the first portion including the first die, the first memory request comprising a read request or a write request;
determining that the first memory request is for an inactive die;
responsive to determining that the first memory request is for the inactive die, buffering the first memory request;
determining that an inactive timer for the first memory die has expired;
responsive to determining that the inactive timer for the first memory die has expired, determining that a second memory die has an active timer that is a longest pending active timer of all other memory die in the enabled subset;
responsive to determining that the second memory die has the longest pending active timer, deactivating the second memory die and activating the first memory die; and
responsive to activating the first memory die:
retrieving the buffered first memory request;
splitting the first memory request into a plurality of component operations selected from a set of possible component operations based upon a type of the first memory request, the set of possible component operations comprising sense, program, transfer to NAND, transfer from NAND, and erase operations;
determining a first power load corresponding to performing a first component operation of the plurality of component operations;
determining whether a sum of the first power load and a current power consumption exceeds a budgeted power consumption for the first portion of the memory system; and
responsive to determining that the sum of the first power load and the current power consumption does not exceed the budgeted power consumption, executing the first component operation of the plurality of component operations.
16. The non-transitory machine-readable medium of claim 15 , including operations to perform:
determining a second power load corresponding to performing a second component operation of the plurality of component operations;
determining whether a sum of the second power load and the current power consumption exceeds the budgeted power consumption; and
responsive to determining that the sum of the second power load and the current power consumption exceeds the budgeted power consumption, buffering the second component operation of the plurality of component operations.
17. The non-transitory machine-readable medium of claim 15 , wherein executing the first component operation of the plurality of component operations results in an increase in current power consumption; and
wherein completion of the first component operation of the plurality of component operations results in a decrease in current power consumption.
18. The non-transitory machine-readable medium of claim 15 , wherein the budgeted power consumption is established for a channel of an individual memory die of multiple memory die of the NAND memory system.