Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors
A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.
1. A method of forming a device, comprising:
forming an array comprising rows and columns of elevationally-extending transistors, an access line interconnecting multiple of the elevationally-extending transistors along individual of the rows;
the transistors individually comprising:
an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between; the channel region comprising an oxide semiconductor; and
a transistor gate operatively laterally proximate the channel region, the transistor gate comprising a portion of an individual of the access lines;
intra-row void space being longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors;
inter-row void space laterally between immediately-adjacent of the rows of the elevationally-extending transistors; and
forming insulator material to bridge across tops of the intra-row void space and to bridge across tops of the inter-row void space and leave the intra-row void space and the inter-row void space there-below.
2. The method of claim 1 wherein forming the insulator material comprises:
depositing the insulator material to cover the intra-row void space and the inter-row void space; and
after the depositing, removing the insulator material back elevationally at least to tops of the upper source/drain regions.
3. The method of claim 2 wherein the removing forms the insulator material and the upper source/drain regions to have respective elevationally-outermost surfaces that are planar and coplanar.
4. The method of claim 1 wherein forming the elevationally-extending transistors comprises:
forming the oxide-semiconductor-channel-comprising material, the gate insulator material, the access lines, the lower source/drains, and the upper source/drain regions running continuously in lines along the individual rows; and
intra-row patterning the lines of oxide-semiconductor-channel-comprising material and lines of the upper source/drain regions to form the channel regions and the upper source/drain regions of the individual transistors.
5. A device comprising:
an array comprising rows and columns of elevationally-extending transistors;
an access line interconnecting multiple of the elevationally-extending transistors along individual of the rows;
the transistors individually comprising:
an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between; the channel region comprising an oxide semiconductor; and
a transistor gate operatively laterally-proximate the channel region, the transistor gate comprising a portion of an individual of the access lines;
intra-row-insulating material longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors;
inter-row-insulating material laterally between immediately-adjacent of the rows of the elevationally-extending transistors; and
at least one of the intra-row-insulating material and the inter-row-insulating material comprising void space.
6. The device of claim 5 wherein the intra-row-insulating material comprises intra-row void space.
7. The device of claim 6 wherein the immediately-intra-row-adjacent transistors have a respective maximum intra-row-separation-distance longitudinally between closest-operative-transistor material, the intra-row void space individually extending longitudinally along at least 50% of said respective maximum intra-row-separation-distance.
8. The device of claim 7 wherein the intra-row void space individually extends longitudinally along at least 75% of said respective maximum intra-row-separation-distance.
9. The device of claim 5 wherein the inter-row-insulating material comprises inter-row void space.
10. The device of claim 5 wherein the intra-row-insulating material comprises intra-row void space and the inter-row-insulating material comprises inter-row void space.
11. The device of claim 10 wherein the intra-row void space and the inter-row void space collectively do not completely surround the channel region of individual of the transistors.
12. The device of claim 5 wherein the transistor gate is over two opposing sides of the channel region.
13. The device of claim 12 wherein the transistor gate laterally surrounds the channel region.
14. The device of claim 12 wherein the transistors individually comprise:
a gate insulator over individual of the two opposing sides of the channel region laterally between the channel region and the transistor gate, the two opposing sides of the channel region individually comprising the oxide semiconductor, an elevationally-elongated void space being laterally between the two opposing sides of the channel region.
15. The device of claim 5 wherein the transistors are elevationally-extending to be vertical or within 10° of vertical.