Input buffer circuit
An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.
1. An apparatus comprising:
first and second voltage terminals;
a first transistor coupled between the first voltage terminal and a first circuit node;
a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control electrode coupled to the first circuit node;
a first current control circuit coupled between the second circuit node and the second voltage terminal, the first current control circuit configured to receive a code signal; and
a fourth transistor coupled to the first voltage terminal, the fourth transistor having a control electrode supplied with a reference voltage.
2. The apparatus of claim 1 , further comprising:
a fifth transistor having a control electrode coupled to the fourth transistor; and
a second current control circuit coupled between the fifth transistor and the second voltage terminal.
3. An apparatus comprising:
first and second voltage terminals;
a first transistor coupled between the first voltage terminal and a first circuit node;
a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control electrode coupled to the first circuit node;
a first current control circuit coupled between the second circuit node and the second voltage terminal, the first current control circuit configured to receive a code signal; and a flip-flop circuit coupled between the first voltage terminal and the second transistor.
4. The apparatus of claim 1 , wherein the flip-flop circuit comprises first and second inverters cross-coupled to each other.
5. An apparatus comprising:
first and second voltage terminals;
a first transistor coupled between the first voltage terminal and a first circuit node;
a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control electrode coupled to the first circuit node;
a first current control circuit coupled between the second circuit node and the second voltage terminal, the first current control circuit configured to receive a code signal; and
a first inverter coupled between the first voltage terminal and the second transistor.
6. An apparatus comprising:
first and second voltage terminals;
a first transistor coupled between the first voltage terminal and a first circuit node;
a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control electrode coupled to the first circuit node;
a first current control circuit coupled between the second circuit node and the second voltage terminal, the first current control circuit configured to receive a code signal;
a fourth transistor coupled between the first voltage terminal and a third circuit node;
a fifth transistor coupled between the first voltage terminal and a fourth circuit node; and
first and second inverters cross-coupled to each other.
7. The apparatus of claim 6 , wherein the first inverter is coupled between the first voltage terminal and the second transistor, and
wherein the second inverter is coupled between the first voltage terminal and the fifth transistor.
8. An apparatus comprising:
first and second voltage terminals;
a first transistor coupled between the first voltage terminal and a first circuit node;
a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control electrode coupled to the first circuit node;
a first current control circuit coupled between the second circuit node and the second voltage terminal, the first current control circuit configured to receive a code signal; and
a fourth transistor coupled to the first voltage terminal,
wherein the first and fourth transistors are configured to receive an input signal and another input signal, respectively.
9. An apparatus comprising:
a first transistor;
a second transistor coupled to the first transistor;
a plurality of third transistors coupled between the second transistor and a voltage terminal;
a fourth transistor coupled to the first transistor;
a fifth transistor coupled to the fourth transistor; and
a plurality of sixth transistors coupled between the fifth transistor and the voltage terminal, wherein the first transistor comprises a control electrode configured to receive an input signal, and
wherein the second transistor comprises a control electrode configured to receive a reference voltage.
10. An apparatus comprising:
a first transistor;
a second transistor coupled to the first transistor;
a plurality of third transistors coupled between the second transistor and a voltage terminal;
a fourth transistor coupled to the first transistor;
a fifth transistor coupled to the fourth transistor;
a plurality of sixth transistors coupled between the fifth transistor and the voltage terminal; and
a flip-flop circuit coupled between another voltage terminal and the second and fifth transistors.
11. The apparatus of claim 10 , wherein the flip-flop circuit comprises first and second inverters cross-coupled to each other.
12. An apparatus comprising:
a first amplifier coupled to first and second circuit nodes;
a first transistor coupled between the first circuit node and a third circuit node;
a plurality of second transistors coupled between the third circuit node and a voltage terminal;
a third transistor coupled between the second circuit node and a fourth circuit node; and
a flip-flop circuit coupled to the first transistor and the third transistor.
13. The apparatus of claim 12 , further comprising:
a current control circuit comprising the plurality of second transistors; and
another current control circuit comprising a plurality of fourth transistors coupled to the fourth circuit node,
wherein the current control circuit is configured to receive a code signal, and
wherein the other current control circuit is configured to receive another code signal.
14. The apparatus of claim 12 , wherein the first transistor comprises a control electrode coupled to the first circuit node, and
wherein the third transistor comprises a control electrode coupled to the second circuit node.
15. The apparatus of claim 12 , further comprising a plurality of fourth transistors coupled between the fourth circuit node and the voltage terminal.