Methods of memory address verification and memory devices employing the same
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.
1. A memory device, comprising a memory controller configured to:
generate, for a data word to be stored at an address in a memory array, a location indicia corresponding to the address; and
send the data word and the location indicia to the memory array for storage.
2. The memory device of claim 1 , wherein the memory controller is further configured to:
command the memory array to read the data word from the address,
receive response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.
3. The memory device of claim 2 , wherein the memory controller is further configured to:
indicate an error if the location indicia of the response data does not correspond to the address.
4. The memory device of claim 2 , wherein the memory controller is further configured to:
output the data word if the location indicia of the response data corresponds to the address.
5. The memory device of claim 1 , wherein the memory controller is further configured to:
verify that a location indicia already stored at the address in the memory array corresponds to the address.
6. The memory device of claim 1 , wherein the location indicia is a hash of the address.
7. The memory device of claim 1 , wherein the address corresponds to a row of the memory array, and wherein the location indicia corresponds to the row.
8. The memory device of claim 1 , wherein the location indicia is the address.
9. The memory device of claim 1 , wherein the memory controller is configured to send the data word and the location indicia to the memory array for storage by appending or prepending the location indicia to the data word.
10. The memory device of claim 1 , wherein the data word comprises a plurality of bits.
11. The memory device of claim 1 , wherein the memory device comprises the memory array.
12. A method of operating a memory device, comprising:
receiving a data word to be stored at an address in a memory array;
generating a location indicia corresponding to the address; and
sending the data word and the location indicia to the memory array for storage.
13. The method of claim 12 , further comprising:
commanding the memory array to read the data word from the address,
receiving response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.
14. The method of claim 13 , further comprising:
indicating an error if the location indicia of the response data does not correspond to the address.
15. The method of claim 13 , further comprising:
outputting the data word if the location indicia of the response data corresponds to the address.
16. The method of claim 12 , further comprising:
generating the location indicia by hashing the address.
17. The method of claim 12 , further comprising:
appending or prepending the location indicia to the data word before sending the data word and the location indicia to the memory array for storage.
18. A memory system, comprising:
a host device; and
a memory device operatively coupled to the host device, the memory device configured to:
receive a data word to be stored at an address in a memory array;
generate a location indicia corresponding to the address; and
send the data word and the location indicia to the memory array for storage.
19. The memory system of claim 18 , wherein the memory device is further configured to:
commanding the memory array to read the data word from the address,
receiving response data from the memory array, and
verify that a location indicia of the response data corresponds to the address.
20. The memory system of claim 18 , wherein the memory device comprises the memory array.