IP Library Granted Patent US 10,692,559
Granted Patent B2
US 10,692,559 · App. 16/177,216 · Granted Jun 23, 2020

Performing an on demand refresh operation of a memory sub-system

Inventor: Michael T. Brady (Loveland, CO)
Assignee: Micron Technology, Inc.
G11C11/40611G06F3/061G06F3/0605G06F3/0632G06F3/0679G06F11/3419G06F12/0246G11C11/4076G11C11/419G11C16/16G06F2201/81G06F2212/1016G06F2212/2022G06F2212/7201G11C2211/4061
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Quick Facts
Patent No.
US 10,692,559
App. No.
16/177,216
Granted
Jun 23, 2020
Kind
B2
Abstract

A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.

Claims (31)

1. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

identify a temporal attribute of user data stored in the memory component;

determine that the identified temporal attribute satisfies a time condition;

upon determining that the identified temporal attribute satisfies the time condition, provide an indication whether a refresh operation of the user data improves performance of the memory component;

receive a user input indicating to perform the refresh operation of the memory component; and

perform the refresh operation of the memory component.

2. The system of claim 1 , wherein the temporal attribute represents an amount of time that has elapsed since the user data was stored in the memory component, wherein to determine that the identified temporal attribute satisfies the time condition, the processing device is to:

determine that the amount of time that has elapsed exceeds a threshold amount of time.

3. The system of claim 1 , wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide at least one of:

the indication identifying that the refresh operation of the user data improves performance of the memory component; or

the indication identifying that the refresh operation of the user data does not improve performance of the memory component.

4. The system of claim 1 , wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide a probability of success of the refresh operation of the user data to improve performance of the memory component.

5. The system of claim 1 , wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to:

provide the indication to a host system coupled to the memory component to identify whether the refresh operation of the user data improves performance of the memory component.

6. The system of claim 1 , wherein to perform the refresh operation of the memory component, the processing device is to:

erase the user data from a first location of the memory component; and

perform a write operation on a second location of the memory component using the user data.

7. The system of claim 6 , wherein the first location is the same as the second location.

8. The system of claim 1 , wherein the processing device is further to:

provide one or more information associated with the refresh operation, the one or more information comprising one or more of:

a number of total refresh operations attempted in association with memory component;

a number of successful refresh operations attempted in association with the memory component;

a number of unsuccessful refresh operations attempted in association with the memory component;

an average time to complete refresh operations attempted in association with the memory component;

a standard deviation of time to complete refresh operations attempted in association with the memory component;

a first status of the refresh operation; or

a second status of a previous refresh operation attempted in association with the memory component.

9. The system of claim 1 , wherein prior to performing the refresh operation of the memory component, the processing device is to:

determine that a time between the refresh operation and a previously performed refresh operation exceeds a threshold time.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: BRADY, MICHAEL T.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047374/0925 →