IP Library Granted Patent US 10,521,383
Granted Patent B1
US 10,521,383 · App. 16/223,057 · Granted Dec 31, 2019

Handling operation collisions in a non-volatile memory

Inventors: Lyle E. Adams (San Jose, CA); Mark Ish (San Ramon, CA); Pushpa Seetamraju (San Jose, CA); Karl D. Schuh (Santa Cruz, CA); Dan Tupy (Roseville, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F13/376G06F3/061G06F3/067G06F3/0659G06F13/1631G06F13/1673
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,521,383
App. No.
16/223,057
Granted
Dec 31, 2019
Kind
B1
Abstract

A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.

Claims (40)

1. A method comprising:

assigning a first operation identifier to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers;

determining whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers;

determining whether the first operation is a read or a write operation; and

updating, in response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

2. The method of claim 1 , wherein the determining whether the first operation collides with the prior operation comprises checking a second data structure for an entry that has an address that matches an address associated with the first operation and has a flag set.

3. The method of claim 1 , wherein the updating comprises replacing a buffer identifier included in the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

4. The method of claim 1 , further comprising, in response to determining that the first operation collides with the prior operation and that the first operation is a write operation, setting a flag associated with the first operation in a second data structure and clearing a flag associated with the prior operation in the second data structure.

5. The method of claim 1 , further comprising:

determining that the prior operation is a read operation; and

updating, in response to determining that the first operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier.

6. The method of claim 1 , further comprising incrementing a counter associated with a buffer identified by a buffer identifier in the first plurality of buffer identifiers.

7. The method of claim 1 , wherein the first data structure is stored in a memory outside of the memory component.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

assign a first operation identifier to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers;

determine whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers;

determine whether the first operation is a read or a write operation; and

update, in response to a determination that that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

9. The non-transitory computer-readable storage medium of claim 8 , wherein to determine whether the first operation collides with the prior operation, the processing device is to check a second data structure for an entry that has an address that matches an address associated with the first operation and has a flag set.

10. The non-transitory computer-readable storage medium of claim 8 , wherein to update the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers, the processing device is to replace a buffer identifier included in the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to, in response to a determination that the first operation collides with the prior operation and that the first operation is a write operation, set a flag associated with the first operation in a second data structure and clear a flag associated with the prior operation in the second data structure.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

determine that the prior operation is a read operation; and

update, in response to determining that the first operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to increment a counter associated with a buffer identified by a buffer identifier in the first plurality of buffer identifiers.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the first data structure is stored in a memory outside of the memory component.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the plurality of memory components, to:

assign a first operation identifier to a first operation directed to the memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers;

determine whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers;

determine whether the first operation is a read or a write operation; and

update, in response to a determination that that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

16. The system of claim 15 , wherein to determine whether the first operation collides with the prior operation, the processing device is to check a second data structure for an entry that has an address that matches an address associated with the first operation and has a flag set.

17. The system of claim 15 , wherein to update the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers, the processing device is to replace a buffer identifier included in the first plurality of buffer identifiers with a buffer identifier included in the second plurality of buffer identifiers.

18. The system of claim 15 , wherein the processing device is further to, in response to a determination that the first operation collides with the prior operation and that the first operation is a write operation, set a flag associated with the first operation in a second data structure and clear a flag associated with the prior operation in the second data structure.

19. The system of claim 15 , wherein the processing device is further to:

determine that the prior operation is a read operation; and

update, in response to determining that the first operation collides with the prior operation and that the prior operation is a read operation, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier.

20. The system of claim 15 , wherein the processing device is further to increment a counter associated with a buffer identified by a buffer identifier in the first plurality of buffer identifiers.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2019
From: ADAMS, LYLE E.; ISH, MARK; SEETAMRAJU, PUSHPA; SCHUH, KARL D.; TUPY, DAN
To: MICRON TECHNOLOGY, INC
Reel/Frame 049393/0776 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Cited By (1)
US 12,613,658