Responding to power loss

1. A method of operating a memory, comprising:

obtaining information indicative of respective data values stored in a plurality of memory cells of the memory corresponding to an address;

programming additional data to the plurality of memory cells;

determining if a power loss to the memory is indicated while programming the additional data to the plurality of memory cells; and

if a power loss to the memory is indicated:

programming a first plurality of differential storage devices responsive to the information indicative of the respective data values stored in the plurality of memory cells;

programming a second plurality of differential storage devices responsive to the address; and

programming a third differential storage device to have a particular value.

2. The method of claim 1 , further comprising:

wherein programming a differential storage device of the first plurality of differential storage devices comprises:

selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of that differential storage device responsive to information indicative of a respective digit of the respective data value stored in a corresponding memory cell of the plurality of memory cells;

wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells of that differential storage device and of the other memory cell of the pair of gate-connected non-volatile memory cells of that differential storage device is representative of the information indicative of the digit of the respective data value stored in the corresponding memory cell of the plurality of memory cells;

wherein programming a differential storage device of the second plurality of differential storage devices comprises:

selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of that differential storage device responsive to information indicative of a corresponding digit of the address;

wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells of that differential storage device and of the other memory cell of the pair of gate-connected non-volatile memory cells of that differential storage device is representative of the information indicative of the corresponding digit of the address; and

wherein programming the third differential storage device comprises:

programming one memory cell of a pair of gate-connected non-volatile memory cells of the third differential storage device;

wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells of the third differential storage device and of the other memory cell of the pair of gate-connected non-volatile memory cells of the third differential storage device is representative of the particular value.

3. The method of claim 1 , further comprising:

if a power loss to the memory is indicated:

programming a fourth plurality of differential storage devices responsive to information indicative of respective data values of the additional data for the plurality of memory cells.

4. The method of claim 1 , wherein programming a particular differential storage device comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of the particular differential storage device, wherein the particular differential storage device is selected from a group consisting of a differential storage device of the first plurality of differential storage devices, a differential storage device of the second plurality of differential storage devices, and the third differential storage device, and wherein programming the one memory cell of the pair of gate-connected non-volatile memory cells comprises:

applying a first voltage level to a first source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells and to a first source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a second voltage level higher than the first voltage level to a gate of the one memory cell of the pair of gate-connected non-volatile memory cells and to a gate of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a third voltage level, higher than the first voltage level and lower than the second voltage level, to a second source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells; and

applying the first voltage level to a second source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells.

5. The method of claim 4 , wherein a combination of the first voltage level, the second voltage level and the third voltage level is selected to cause charge to accumulate in a data-storage structure of the one memory cell during programming of the one memory cell.

6. A method of operating a memory, comprising:

obtaining information indicative of respective data values stored in a plurality of memory cells of the memory corresponding to an address, each respective data value comprising more than one digit of data;

programming additional data to the plurality of memory cells;

determining if a power loss to the memory is indicated while programming the additional data to the plurality of memory cells; and

if a power loss to the memory is indicated:

programming a first plurality of differential storage devices responsive to the information indicative of the respective data values stored in the plurality of memory cells such that a first subset of the first plurality of differential storage devices is programmed responsive to a particular digit of data of each of the respective data values stored in the plurality of memory cells and a different subset of the first plurality of differential storage devices is programmed responsive to a different digit of data of each of the respective data values stored in the plurality of memory cells;

programming a second plurality of differential storage devices responsive to the address; and

programming a third differential storage device to have a particular value.

7. The method of claim 6 , wherein the plurality of memory cells is a first plurality of memory cells, the address is a first address, and the additional data is first additional data, the method further comprising:

obtaining information indicative of respective data values stored in a second plurality of memory cells of the memory corresponding to a second address, each respective data value of the second plurality of memory cells comprising more than one digit of data;

programming second additional data to the second plurality of memory cells;

determining if a power loss to the memory is indicated while programming the second additional data to the second plurality of memory cells; and

if a power loss to the memory is indicated while programming the second additional data to the second plurality of memory cells:

programming a fourth plurality of differential storage devices responsive to the information indicative of the respective data values stored in the second plurality of memory cells such that a first subset of the fourth plurality of differential storage devices is programmed responsive to a particular digit of data of each of the respective data values stored in the second plurality of memory cells and a different subset of the fourth plurality of differential storage devices is programmed responsive to a different digit of data of each of the respective data values stored in the second plurality of memory cells;

programming a fifth plurality of differential storage devices responsive to the second address; and

programming a sixth differential storage device to have a particular value.

8. The method of claim 7 , wherein programming the first additional data to the first plurality of memory cells and programming the second additional data to the second plurality of memory cells occur concurrently.

9. The method of claim 7 , wherein determining that a power loss to the memory is indicated while programming the first additional data to the first plurality of memory cells determines that a power loss to the memory is indicated while programming the second additional data to the second plurality of memory cells.

10. The method of claim 6 , wherein programming a particular differential storage device comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of the particular differential storage device, wherein the particular differential storage device is selected from a group consisting of a differential storage device of the first plurality of differential storage devices, a differential storage device of the second plurality of differential storage devices, and the third differential storage device.

11. A method of operating a memory, comprising:

obtaining information indicative of respective data values stored in a first plurality of memory cells of the memory corresponding to a first address of the memory;

programming additional data to the plurality of memory cells;

determining if a power loss to the memory is indicated while programming the additional data to the first plurality of memory cells; and

if a power loss to the memory is indicated:

programming a first plurality of differential storage devices responsive to the information indicative of the respective data values stored in the first plurality of memory cells;

programming a second plurality of differential storage devices responsive to the first address;

programming a third differential storage device to have a particular value; and

after programming the first plurality of differential storage devices, after programming the second plurality of differential storage devices, and after programming the third differential storage device:

initializing operation of the memory;

determining whether the third differential storage device has the particular value;

if the third differential storage device has a value different than the particular value, continuing with normal operation of the memory; and

if the third differential storage device has the particular value:

reading address data comprising the first address of the memory from the second plurality of differential storage devices;

copying data from the first plurality of differential storage devices to a second plurality of memory cells corresponding to a second address of the memory;

updating a mapping table entry referencing the first address to reference the second address; and

erasing data from the first plurality of memory cells.

12. The method of claim 11 , wherein determining whether the third differential storage device has the particular value comprises transferring the value of the third differential storage device to a flag register of a status register of the memory, and determining whether the flag register has the particular value.

13. The method of claim 12 , wherein determining whether the flag register has the particular value comprises using a controller external to the memory to read the flag register.

14. The method of claim 13 , wherein reading the address data comprises reading the address data and transferring the address data to the controller external to the memory.

15. The method of claim 11 , wherein copying the data from the first plurality of differential storage devices to the second plurality of memory cells corresponding to the second address of the memory further comprises copying data from memory cells related to the first address and mutually exclusive of the first plurality of memory cells to other memory cells related to the second address and mutually exclusive of the second plurality of memory cells.

16. The method of claim 15 , wherein copying the data from the memory cells related to the first address and mutually exclusive of the first plurality of memory cells to the other memory cells related to the second address and mutually exclusive of the second plurality of memory cells comprises copying data from memory cells of a same block of memory cells as the first plurality of memory cells to memory cells of a same block of memory cells as the second plurality of memory cells.

17. The method of claim 11 , further comprising:

wherein programming a particular differential storage device of the first plurality of differential storage devices comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of that differential storage device;

wherein programming a particular differential storage device of the second plurality of differential storage devices comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of that differential storage device; and

wherein programming the third differential storage device comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of the third differential storage device.

18. The method of claim 11 , wherein programming the third differential storage device to have the particular value comprises programming one memory cell of a pair of gate-connected non-volatile memory cells of the third differential storage device, and wherein programming the one memory cell of the pair of gate-connected non-volatile memory cells comprises:

applying a first voltage level to a first source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells and to a first source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a second voltage level higher than the first voltage level to a gate of the one memory cell of the pair of gate-connected non-volatile memory cells and to a gate of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a third voltage level, higher than the first voltage level and lower than the second voltage level, to a second source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells; and

applying the first voltage level to a second source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells.

19. The method of claim 18 , wherein a combination of the first voltage level, the second voltage level and the third voltage level is selected to cause charge to accumulate in a data-storage structure of the one memory cell during programming of the one memory cell.

20. The method of claim 13 , wherein the combination of the first voltage level, the second voltage level and the third voltage level is further selected to inhibit charge accumulation in a data-storage structure of the other memory cell during programming of the one memory cell.