Apparatuses and methods for providing multiphase clock signals
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
1. An apparatus, comprising:
a quadrant divider circuit configured to receive first and second strobe signals and provide oscillating quadrature clock signals, and wherein the quadrant divider circuit is further configured to enter a self-oscillation mode to continue providing the oscillating quadrature clock signals responsive to the quadrature clock signals having respective clock levels corresponding to an initial condition and the first and second strobe signals clamped to a same clock level thereafter.
2. The apparatus of claim 1 wherein the oscillating quadrature clock signals have a clock frequency one-half a clock frequency of the first and second strobe signals.
3. The apparatus of claim 1 wherein the first and second strobe signals are complementary prior to being clamped to the same clock level.
4. The apparatus of claim 1 , further comprising:
first, second, third, and fourth bias controlled inverter circuits, each coupled to receive a respective one of the quadrature clock signals from the quadrant divider circuit and provide a respective phase signal;
a plurality of receiver circuits, each coupled to a respective data terminal and configured to capture respective data responsive to the phase signals from the first, second, third, and fourth bias controlled inverter circuits and further configured to provide the captured data; and
data read/write control circuitry configured to receive the captured data from the plurality of receiver circuits and further configured to provide the data to be stored in memory.
5. The apparatus of claim 1 , further comprising a plurality of bias controlled inverter circuits coupled to the quadrant divider circuit.
6. The apparatus of claim 5 , wherein the plurality of bias controlled inverter circuits are configured to provide a plurality of phase signals responsive to the quadrature clock signals.
7. The apparatus of claim 1 , further comprising data read/write control circuitry configured to provide data to be stored in memory responsive, at least in part, to the oscillating quadrature clock signals.
8. The apparatus of claim 1 , wherein the initial condition includes an initial self-oscillation condition of the quadrature clock signals having respective states.
9. The apparatus of claim 1 , wherein each of the quadrature clock signals has a level corresponding to the initial condition of the first and second strobe signals having high and low clock levels, respectively.
10. The apparatus of claim 1 , further comprising a plurality of receiver circuits, each configured to capture respective data based, at least in part, on the oscillating quadrature clock signals and further configured to provide the captured data.
11. An apparatus, comprising:
a quadrant divider circuit configured to receive first and second strobe signals and configured to provide oscillating quadrature clock signals; and
a plurality of bias controlled inverter circuits configured to provide phase signals responsive to the quadrature clock signals,
wherein the oscillating quadrature clock signals are generated by the quadrant divider circuit responsive, at least in part, to the first and second strobe signals clamped to a same clock level.
12. The apparatus of claim 11 , wherein, prior to being clamped to the same clock level, the first and second strobe signals have levels based on an initial condition.
13. The apparatus of claim 11 , wherein the first and second strobe signals are complementary prior to being clamped to the same clock level.
14. The apparatus of claim 11 , wherein the oscillating quadrature clock signals have a clock frequency one-half a clock frequency of the first and second strobe signals.
15. The apparatus of claim 11 , wherein the oscillating quadrature clock signals are self-oscillating output signals.
16. The apparatus of claim 11 , wherein the oscillating quadrature clock signals provided by the quadrant divider circuit have respective states corresponding to an initial self-oscillation condition.
17. An apparatus, comprising:
a quadrant divider circuit comprising a plurality of clocked inverter circuits coupled in a ring, the quadrant divider circuit configured to receive first and second strobe signals and configured to provide oscillating quadrature clock signals; and
a plurality of bias controlled inverter circuits configured to provide phase signals responsive to the oscillating quadrature clock signals,
wherein the oscillating quadrature clock signals are provided based, at least in part, on an initial condition.
18. The apparatus of claim 17 , wherein the first and second strobe signals are complementary prior to being clamped to a same clock level.
19. The apparatus of claim 17 , wherein the initial condition includes an initial self-oscillation condition of the quadrature clock signals having respective states.
20. The apparatus of claim 17 , wherein the quadrant divider circuit is further configured to enter a self-oscillation mode to provide the oscillating quadrature clock signals, and
wherein the oscillating quadrature clock signals have a clock frequency one-half a clock frequency of the first and second strobe signals.