IP Library Granted Patent US 10,877,832
Granted Patent B2
US 10,877,832 · App. 16/170,748 · Granted Dec 29, 2020

Data-structure based dynamic program targeting control

Inventors: Michael Sheperek (Longmont, CO); Bruce A. Liikanen (Berthoud, CO); Larry J. Koudele (Erie, CO); James P. Crowley (Longmont, CO); Stuart A. Bell (Fort Collins, CO)
Assignee: Micron Technology, Inc.
G06F11/076G06F3/064G06F3/0619G06F3/0673G06F11/0727G06F11/0793
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Quick Facts
Patent No.
US 10,877,832
App. No.
16/170,748
Granted
Dec 29, 2020
Kind
B2
Abstract

Feedback relating to errors in memory operations on a plurality of memory cells is received by a memory sub-system. At least one processing level corresponding to a program distribution is updated based on the feedback to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of cells. The updating of the at least one processing level is based on information for the at least one processing level that is stored in a data-structure.

Claims (38)

1. A system, comprising:

a memory component including a plurality of memory cells;

a data-structure corresponding to the plurality of memory cells; and

a processing device, operatively coupled to the memory component and the data-structure, to:

receive feedback related to errors in memory operations on the plurality of memory cells, the feedback including a first feedback portion corresponding to a first page type and a second feedback portion corresponding to a second page type that is different from the first page type, and

update, based on the feedback and information stored in the data-structure, at least one processing level corresponding to a respective program distribution to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of memory cells,

wherein the information stored in the data structure includes a plurality of program distribution rules for shifting the at least one processing level based on a comparison between the first feedback portion and the second feedback portion.

2. The system of claim 1 , wherein the data-structure is a look-up-table.

3. The system of claim 1 , wherein the error measure is a bit error rate and the feedback is an error count.

4. The system of claim 1 , wherein the information stored in the data-structure includes trim information that is used for controlling the shifting of the at least one processing level, the trim information including at least one of a magnitude, a direction, or a bandwidth of the shifting.

5. The system of claim 1 , wherein the adjusting of the error measure equalizes the error measure between pages of the plurality of memory cells, and

wherein the adjusting of the read window budget equalizes read window budgets within the page.

6. The system of claim 1 , wherein the information for the at least one processing level in the data-structure is updateable.

7. The system of claim 1 , wherein the at least one processing level corresponds to a program-verify level.

8. The system of claim 1 , wherein the first page type includes a first read window budget and a second read window budget, and wherein each rule of the plurality of program distribution rules includes a plurality of sub-rules for shifting the at least one processing level based on a comparison of the first read window budget to the second read window budget.

9. A method, comprising:

receiving feedback related to errors in memory operations on a plurality of memory cells, the feedback including a first feedback portion corresponding to a first page type and a second feedback portion corresponding to a second page type that is different from the first page type, and

updating, based on the feedback and information stored in a data structure, at least one processing level corresponding to a respective program distribution to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of memory cells,

wherein the information stored in the data structure includes a plurality of program distribution rules for shifting the at least one processing level based on a comparison between the first feedback portion and the second feedback portion.

10. The method of claim 9 , wherein the data structure is a look-up-table.

11. The method of claim 9 , wherein the error measure is a bit error rate and the feedback is an error count.

12. The method of claim 9 , wherein the information stored in the data-structure includes trim information that is used for controlling the shifting of the at least one processing level, the trim information including at least one of a magnitude, a direction, or a bandwidth of the shifting.

13. The method of claim 9 , wherein the adjusting of the error measure equalizes the error measure between pages of the plurality of memory cells, and

wherein the adjusting of the read window budget equalizes read window budgets within the page.

14. The method of claim 9 , wherein the information for the at least one processing level in the data-structure is updateable.

15. The method of claim 9 , wherein the at least one processing level corresponds to a program-verify level.

16. The method of claim 9 , wherein the first page type includes a first read window budget and a second read window budget, and wherein each rule of the plurality of program distribution rules includes a plurality of sub-rules for shifting the at least one processing level based on a comparison of the first read window budget to the second read window budget.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive feedback related to errors in memory operations on a plurality of memory cells, the feedback including a first feedback portion corresponding to a first page type and a second feedback portion corresponding to a second page type that is different from the first page type, and

update, based on the feedback and information stored in a data-structure, at least one processing level corresponding to a program distribution to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of memory cells,

wherein the information stored in the data structure includes a plurality of program distribution rules for shifting the at least one processing level based on a comparison between the first feedback portion and the second feedback portion.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the data structure is a look-up-table.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the error measure is a bit error rate and the feedback is an error count.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the information stored in the data-structure includes trim information that is used for controlling shifting of the at least one processing level, the trim information including at least one of a magnitude, a direction, or a bandwidth of the shifting.

21. The non-transitory computer-readable storage medium of claim 17 , wherein the adjusting of the error measure equalizes the error measure between pages of the plurality of memory cells, and

wherein the adjusting of the read window budget equalizes read window budgets within the page.

22. The non-transitory computer-readable storage medium of claim 17 , wherein the information for the at least one processing level in the data-structure is updateable.

23. The non-transitory computer-readable storage medium of claim 17 , wherein the first page type includes a first read window budget and a second read window budget, and wherein each rule of the plurality of program distribution rules includes a plurality of sub-rules for shifting the at least one processing level based on a comparison of the first read window budget to the second read window budget.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2018
From: SHEPEREK, MICHAEL; LIIKANEN, BRUCE A.; KOUDELE, LARRY J.; CROWLEY, JAMES P.; BELL, STUART A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047313/0319 →