IP Library Granted Patent US 10,502,896
Granted Patent B2
US 10,502,896 · App. 16/247,996 · Granted Dec 10, 2019

Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

Inventor: Roy E. Meade (Oakland, CA)
Assignee: Micron Technology, Inc.
G02B6/136G02B6/122H01L21/76283G02B2006/12061H01L21/84
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Quick Facts
Patent No.
US 10,502,896
App. No.
16/247,996
Granted
Dec 10, 2019
Kind
B2
Abstract

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

Claims (14)

1. A method of forming an integrated structure, the method comprising:

forming a shallow trench isolation region in a first semiconductor substrate;

filing a trench of the shallow trench isolation region with a first dielectric material having a first index of refraction;

forming a waveguide on a second substrate, wherein the second substrate includes a second dielectric material, wherein the waveguide is formed of a semiconductor material over the second dielectric material, and wherein the semiconductor material has a second index of refraction greater than the first index of refraction; and

attaching the second substrate to the first semiconductor substrate, wherein the second dielectric material faces the first substrate and wherein the waveguide is located over the shallow trench isolation region,

wherein the shallow trench isolation region comprises silicon dioxide within the trench.

2. The method according to claim 1 , wherein a combined thickness of the second dielectric material and the shallow trench isolation region is at least 1000 nm.

3. The method according to claim 1 , wherein the first semiconductor substrate and the second substrate each comprises silicon.

4. The method according to claim 1 , wherein the waveguide comprises a core region surrounded by a cladding region, the cladding region being formed at least in part by the second dielectric material.

5. The method according to claim 4 , wherein the core region comprises silicon and the cladding region comprises silicon dioxide.

6. The method according to claim 1 , further comprising an area of the semiconductor material of the second substrate on which an electronic circuit element is formed.

7. The method according to claim 1 , wherein the first semiconductor substrate and the second substrate together form a silicon-on-insulator structure.

8. The method according to claim 1 , further comprising a third dielectric material over the semiconductor material of the second substrate.

9. The method according to claim 8 , wherein the third dielectric material is part of an interlayer dielectric structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →