Microelectronic devices including capacitor structures and methods of forming microelectronic devices
View Patent ↗A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.
1. A microelectronic device, comprising:
at least one capacitor structure comprising an active region comprising a central region surrounded by a peripheral region, the active region comprising opposing field edges parallel to a first horizontal direction;
a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction;
a first dielectric material overlying at least a portion of the peripheral region of the active region and adjacent to at least one of the opposing field edges or the opposing gate edges; and
a second dielectric material overlying the central region of the active region and abutting portions of the first dielectric material, the second dielectric material fully surrounded on all sides by the first dielectric material, each of the first dielectric material and the second dielectric material having a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction, wherein the height of the second dielectric material is less than the height of the first dielectric material.
2. The microelectronic device of claim 1 , further comprising contacts located adjacent to at least two peripheral edges of the active region, the contacts being located external to at least one of the opposing field edges or the opposing gate edges.
3. The microelectronic device of claim 1 , wherein the second dielectric material is located overlying the central region without overlying the peripheral region and the first dielectric material is located overlying at least a portion of the peripheral region without overlying the central region.
4. The microelectronic device of claim 1 , wherein the opposing gate edges are located internal to opposing side edges of the active region parallel to the second horizontal direction, the first dielectric material located between the second dielectric material and the opposing gate edges.
5. The microelectronic device of claim 1 , wherein the first dielectric material is adjacent to the opposing gate edges without being adjacent to the opposing field edges.
6. The microelectronic device of claim 1 , further comprising a gap between adjacent capacitor structures, wherein the first dielectric material comprises a narrow ridge of material extending between the second dielectric material and the gap.
7. A microelectronic device, comprising:
at least one capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction;
a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction;
a first dielectric material adjacent to at least one of the opposing field edges or the opposing gate edges; and
a second dielectric material adjacent to the active region and abutting portions of the first dielectric material, each of the first dielectric material and the second dielectric material having a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction, wherein the height of the second dielectric material is less than the height of the first dielectric material, wherein the first dielectric material extends between the second dielectric material of adjacent capacitor structures such that all intermediary regions between respective active regions of adjacent capacitor structures are fully covered with the first dielectric material and the second dielectric material is fully surrounded on all sides by the first dielectric material.
8. The microelectronic device of claim 1 , wherein the gate region comprises a semiconductor material and a conductive material overlying the semiconductor material, the semiconductor material comprising a polysilicon material and the conductive material comprising a silicided tungsten material.
9. The microelectronic device of claim 1 , wherein the second dielectric material comprises a threshold voltage magnitude that is lower than a threshold voltage magnitude of the first dielectric material.
10. The microelectronic device of claim 9 , wherein the first dielectric material including a first resistance comprises a low-voltage oxide material and the second dielectric material including a second resistance comprises a super low voltage oxide material, the second resistance of the second dielectric material being relatively lower than the first resistance of the first dielectric material.
11. The microelectronic device of claim 1 , further comprising isolation regions separating adjacent capacitor structures, wherein sidewalls of the isolation regions abut portions of the first dielectric material at a location external to an interface between the first dielectric material and the second dielectric material on individual capacitor structures.
12. The microelectronic device of claim 1 , wherein one or more of the capacitor structures are electrically connected between a power supply electrode and a ground electrode.
13. The microelectronic device of claim 11 , wherein the gate region comprises a conductive material overlying a polysilicon material such that edges of at least one of the conductive material or the polysilicon material are self-aligned with the interface between the first dielectric material and the second dielectric material.
14. A method of forming a microelectronic device, comprising:
forming a first dielectric material overlying at least a portion of a peripheral region of an active region of a capacitor structure, the active region comprising opposing field edges parallel to a first horizontal direction;
removing a portion of the first dielectric material from a central region of the active region that is surrounded by the peripheral region;
forming a second dielectric material overlying the central region of the active region and abutting portions of the first dielectric material, the second dielectric material fully surrounded on all sides by the first dielectric material, each of the first dielectric material and the second dielectric material having a height in a vertical direction transverse to the first horizontal direction, the height of the second dielectric material being less than the height of the first dielectric material; and
forming a gate region overlying at least one of the first dielectric material or the second dielectric material, the gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction and the vertical direction, the first dielectric material adjacent to at least one of the opposing field edges or the opposing gate edges.
15. The method of claim 14 , wherein forming the first dielectric material and the second dielectric material comprises using a dual-oxide process.
16. The method of claim 14 , wherein forming the first dielectric material comprises:
patterning the first dielectric material to form elongated portions parallel to the first horizontal direction adjacent to the opposing field edges; and
patterning the first dielectric material to form elongated portions parallel to the second horizontal direction adjacent to the opposing gate edges.
17. The method of claim 14 , wherein removing the portion of the first dielectric material comprises removing a portion of the first dielectric material overlying the central region to expose substantially an entire portion of the central region designated for the second dielectric material.
18. The method of claim 14 , further comprising forming isolation regions between adjacent capacitor structures, the isolation regions being formed such that sidewalls thereof are directly adjacent to the second dielectric material on at least two sides.
19. The method of claim 18 , wherein forming the gate region comprises:
forming a semiconductor material comprising polysilicon prior to forming the isolation regions;
forming a conductive material comprising silicided tungsten material overlying the semiconductor material after forming the isolation regions; and
removing portions of each of the semiconductor material and the conductive material to form the gate region without patterning the semiconductor material and the conductive material.
20. The method of claim 19 , wherein forming the semiconductor material and the conductive material comprises self-aligning portions thereof with an interface between the first dielectric material and the second dielectric material.