IP Library Granted Patent US 10,795,576
Granted Patent B2
US 10,795,576 · App. 16/177,985 · Granted Oct 6, 2020

Data relocation in memory

Inventor: Neal A. Galbo (Boca Raton, FL)
Assignee: Micron Technology, Inc.
G06F3/0604G06F3/0646G06F3/0673
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Quick Facts
Patent No.
US 10,795,576
App. No.
16/177,985
Granted
Oct 6, 2020
Kind
B2
Abstract

The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.

Claims (56)

1. An apparatus, comprising:

a memory having a plurality of physical units of memory cells, wherein:

each of the physical units has a different sequential physical address associated therewith;

a first number of the physical units have data stored therein; and

a second number of the physical units do not have data stored therein, wherein the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence; and

circuitry configured to relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.

2. The apparatus of claim 1 , wherein the circuitry is configured to change the second number of the physical units that do not have data stored therein.

3. The apparatus of claim 1 , wherein the circuitry is configured to randomize logical addresses associated with the first number of physical units that have data stored therein after the data has been relocated to the last of the consecutive physical addresses associated with the second number of physical units.

4. The apparatus of claim 1 , wherein:

the memory includes an additional plurality of physical units of memory cells, wherein:

each of the additional physical units has a different sequential physical address associated therewith;

a first number of the additional physical units have data stored therein; and

a second number of the additional physical units do not have data stored therein, wherein the physical address associated with each respective one of the second number of additional physical units is a different consecutive physical address in the sequence; and

the apparatus includes additional circuitry configured to relocate the data stored in the physical unit of the first number of additional physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of additional physical units, to the last of the consecutive physical addresses associated with the second number of additional physical units.

5. The apparatus of claim 1 , wherein:

the circuitry includes a counter configured to count a number of program operations being performed on the memory; and

the circuitry is configured to initiate the relocation of the data in response the counter reaching a particular number of program operations performed on the memory.

6. The apparatus of claim 1 , wherein the circuitry includes a register configured to store a logical address associated with the physical unit of the first number of physical units whose physical address is the first of the physical addresses in the sequence.

7. The apparatus of claim 1 , wherein the circuitry comprises hardware.

8. The apparatus of claim 1 , wherein the circuitry comprises software.

9. A method of operating memory, comprising:

relocating data stored in a first physical unit of the memory to a second physical unit of the memory, wherein:

the first physical unit of the memory is one of a plurality of physical units of the memory that have data stored therein and have different physical addresses associated therewith;

the second physical unit of the memory is one of a plurality of physical units of the memory that do not have data stored therein and have different sequential physical addresses associated therewith;

the physical address associated with the first physical unit of the memory is immediately before the first of the sequential physical addresses; and

the physical address associated with the second physical unit of the memory is the last of the sequential physical addresses.

10. The method of claim 9 , wherein the method includes using algebraic mapping to identify the physical address associated with the second physical unit to which the data stored in the first physical unit of the memory has been relocated.

11. The method of claim 10 , wherein the method includes using the algebraic mapping to identify the physical address associated with the second physical unit to which the data stored in the first physical unit of the memory has been relocated during an operation to sense the relocated data.

12. The method of claim 9 , wherein the method includes relocating the data stored in the first physical unit of the memory to the second physical unit of the memory responsive to a particular number of program operations being performed on the memory.

13. The method of claim 9 , wherein:

relocating the data stored in the first physical unit of the memory to the second physical unit of the memory results in:

the first physical unit of the memory becoming the physical unit of the memory that does not have data stored therein and has the first of the sequential physical addresses associated therewith; and

a third physical unit of the memory becoming the physical unit of the memory that does not have data stored therein and has the last of the sequential physical addresses associated therewith; and

the method further includes relocating data stored in a fourth physical unit of the memory to the third physical unit of the memory, wherein the physical address associated with the fourth physical unit of the memory is immediately before the physical address associated with the first physical unit of the memory.

14. An apparatus, comprising:

a memory having a plurality of groups of memory cells, wherein:

each of the groups includes a plurality of physical units of memory cells;

each of the physical units of each respective group has a different sequential physical address associated therewith;

a first number of the physical units of each respective group have data stored therein; and

a second number of the physical units of each respective group do not have data stored therein, wherein the physical address associated with each respective one of the second number of physical units of each respective group is a different consecutive physical address in the sequence; and

circuitry configured to, for each respective group, relocate the data stored in the physical unit of the first number of physical units of that group, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units of that group, to the last of the consecutive physical addresses associated with the second number of physical units of that group.

15. The apparatus of claim 14 , wherein the circuitry comprises separate circuitry for each respective group.

16. The apparatus of claim 14 , wherein each of the physical units of each respective group have a same size.

17. The apparatus of claim 14 , wherein the second number of the physical units of each respective group that do not have data stored therein comprises a prime number of physical units.

18. The apparatus of claim 14 , wherein the memory comprises three-dimensional cross-point memory.

19. A method of operating memory, comprising:

changing a quantity of physical units of the memory that do not have data stored therein, wherein the physical units of the memory that do not have data stored therein have different sequential physical addresses associated therewith; and

relocating data stored in a physical unit of the memory to one of the physical units of the memory that do not have data stored therein after changing the quantity of physical units that do not have data stored therein, wherein:

a physical address associated with the physical unit of the memory from which the stored data is relocated is immediately before the first of the sequential physical addresses; and

the physical address associated with the physical unit of the memory to which the stored data is relocated is the last of the sequential physical addresses.

20. The method of claim 19 , wherein the method includes relocating the data stored in the physical unit of the memory to the one of the physical units of the memory that do not have data stored therein without using a table.

21. The method of claim 19 , wherein the method includes changing the quantity of physical units of the memory that do not have data stored therein based, at least in part, on an average endurance of the memory.

22. The method of claim 19 , wherein the method includes changing the quantity of physical units of the memory that do not have data stored therein based, at least in part, on a workload of the memory.

23. The method of claim 19 , wherein the method includes changing the quantity of physical units of the memory that do not have data stored therein based, at least in part, on a type of the memory.

24. The method of claim 19 , wherein changing the quantity of physical units of the memory that do not have data stored therein includes increasing the quantity of physical units of the memory that do not have data stored therein.

25. The method of claim 19 , wherein changing the quantity of physical units of the memory that do not have data stored therein includes decreasing the quantity of physical units of the memory that do not have data stored therein.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2018
From: GALBO, NEAL A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047385/0718 →