Secure data removal

1. A storage system comprising:

a group of multi-level memory cells, each multi-level memory cell comprising multiple pages; and

control circuitry configured to:

receive an indication to selectively overwrite first data stored on a first page of a first subset of the group of multi-level memory cells;

determine, in response the indication to selectively overwrite the first data, a second subset of memory cells from the first subset that, in response to programming from a first level to a second level, will alter a read output of the first data on the first page and maintain a read output of the remaining of the multiple pages; and

program the second subset of memory cells from the first level to the second level to securely remove the first data stored on the first page while maintaining data on the remaining of the multiple pages.

2. The storage system of claim 1 ,

wherein the group of multi-level memory cells comprises a group of triple-level memory cells, each triple-level memory cell defining three pages and eight levels, wherein the three pages comprise a lower page, an upper page, and an extra, page, and wherein the eight levels include level 0 (L0) through level 7 (L7), and

wherein the second level is a successive level to the first level.

3. The storage system of claim 2 ,

wherein the first page is the lower page and the remaining of the multiple pages include the upper page and the extra page,

wherein, to determine the second subset of memory cells for first data stored on the lower page of the first subset of memory cells, the control circuitry is configured to:

identify memory cells from the first subset of memory cells programmed to level 3 (L3), and

wherein, to program the second subset of memory cells, the control circuitry is configured to:

program the identified memory cells from the subset of memory cells programmed to L3 to level 4 (L4).

4. The storage system of claim 3 ,

wherein each triple-level memory cell comprises seven read levels, including:

read level 3 (RL3) between level 2 (L2) and L3; and

read level 4 (RL4) between L3 and L4,

wherein, to identify memory cells from the first subset of memory cells programmed to L3, the control circuit is configured to:

read memory cells from the first subset of memory cells at RL3 in a first read operation;

read memory cells from first subset of memory cells at RL4 in a second read operation; and

perform an exclusive OR (XOR) data operation on the results of the first and second read operations, and

wherein the control circuitry is configured to determine the second subset of memory cells using the results of the XOR data operation.

5. The storage system of claim 2 ,

wherein the first page is the upper page and the remaining of the multiple pages include the lower page and the extra page,

wherein, to determine the second subset of memory cells for first data stored on the upper page of the first subset of memory cells, the control circuitry is configured to:

identify memory cells from the first subset of memory cells programmed to level 1 (L1), and

wherein, to program the second subset of memory cells, the control circuitry is configured to:

program the identified memory cells from the first subset of memory cells programmed to L1 to level 2 (L2).

6. The storage system of claim 5 ,

wherein each triple-level memory cell comprises seven read levels, including:

read level 1 (RL1) between L0 and L1; and

read level 2 (RL2) between L1 and L2,

wherein, to identify memory cells from the first subset of memory cells programmed to L1, the control circuit is configured to:

read memory cells from the first subset of memory cells at RL1 in a first read operation;

read memory cells from the first subset of memory cells at RL2 in a second read operation; and

perform an exclusive OR (XOR) data operation on the results of the first and second read operations, and

wherein the control circuitry is configured to determine the second subset of memory cells using the results of the XOR data operation.

7. The storage system of claim 2 ,

wherein the first page is the extra page and the remaining of the multiple pages include the lower page and the upper page,

wherein, to determine the second subset of memory cells for first data stored on the extra page of the first subset of memory cells, the control circuitry is configured to:

identify memory cells from the first subset of memory cells programmed to L0, and

wherein, to program the second subset of memory cells, the control circuitry is configured to:

program the identified memory cells from the first subset of memory cells programmed to L0 to level 1 (L1).

8. The storage system of claim 7 ,

wherein each triple-level memory cell comprises seven read levels, including read level 1 (RL1) between L0 and L1,

wherein, to identify memory cells from the first subset of memory cells programmed to L0, the control circuit is configured to:

read memory cells from the first subset of memory cells at RL1 in a first read operation, and

wherein the control circuitry is configured to determine the second subset memory cells using the results of the first read operation.

9. The storage system of claim 1 ,

wherein the group of multi-level memory cells comprises a group of two-level memory cells, each two-level memory cell defining two pages and four levels, wherein the two pages comprise a lower page and an upper page, and wherein the four levels include level 0 (L0) through level 3 (L3), and

wherein the second level is a successive level to the first level.

10. The storage system of claim 9 ,

wherein the first page is the lower page and the remaining of the multiple pages includes the upper page,

wherein, to determine the second subset of memory cells for first data stored on the lower page of the first subset of memory cells, the control circuitry is configured to:

identify memory cells from the first subset of memory cells programmed to level 1 (L1), and

wherein, to program e second subset of memory cells, the control circuitry is configured to:

program the identified memory cells from the first subset of memory cells programmed to L1 to level 2 (L2).

11. The storage system of claim 10 ,

wherein each two-level memory cell comprises three read levels, including:

read level 1 (RL1) between L0 and L1; and

read level 2 (RL2) between L1 and L2,

wherein, to identify memory cells from the first subset of memory cells programmed to L1, the control circuit is configured to:

read memory cells from the first subset of memory cells at RL2 in a first read operation;

read memory cells from the first subset of memory cells at RL1 in a second read operation; and

perform an exclusive OR (XOR) data operation on the results of the first and second read operations, and

wherein the control circuitry is configured to determine the second subset of memory cells using the results of the XOR data operation.

12. The storage system of claim 9 ,

wherein the first page is the upper page and the remaining of the multiple pages includes the lower page,

wherein, to determine the second subset of memory cells for first data stored on the upper page of the first subset of memory cells, the control circuitry is configured to:

identify memory cells from the first subset of memory cells programmed to L0, and

wherein, to program the second subset of memory cells, the control circuitry is configured to:

program the identified memory cells from the first subset of memory cells programmed to L0 to level 1 (L1).

13. The storage system of claim 12 ,

wherein each two-level memory cell comprises three read levels, including read level 1 (RL1) between L0 and L1,

wherein, to identify memory cells from the first subset of memory cells programmed to L0, the control circuit is configured to:

read memory cells from the first subset of memory cells at RL1 in a first read operation, and

wherein the control circuitry is configured to determine the second subset of memory cells using the results of the first read operation.

14. The storage system of claim 1 ,

wherein the group of multi-level memory cells comprises a group of quad-level memory cells, each quad-level memory cell defining four pages and sixteen levels, wherein the four pages comprise a lower page, an upper page, an extra page, and a top page, and wherein the sixteen levels include level 0 (L0) through level 15 (L15),

wherein the first page is one of the four pages and the remaining of the multiple pages include the remaining three of the four pages, and

wherein the second level is a successive level to the first level.

15. The storage system of claim 1 ,

wherein the control circuitry is configured to, in response to moving the first data from a first location to a second location on the storage system, provide the indication to securely remove the first data stored at the first location.

16. The storage system of claim 1 ,

wherein the control circuitry is configured to, in response the indication to selectively overwrite the first data, provide at least one soft erase pulse to the first data stored on the first page to induce distribution overlaps.

17. The storage system of claim 1 , comprising:

a host device comprising a host processor and a group of volatile memory cells;

a host interface configured to enable communication between the storage system and the host device;

a memory controller; and

a memory device comprising a device controller the group of multi-level memory cells, wherein the group of multi-level memory cells includes a group of multi-level, non-volatile memory cells,

wherein the control circuitry includes at least one of the memory controller or the device controller, and

wherein the multiple levels of each multi-level memory cell defines the multiple pages.

18. A method comprising:

receiving, at control circuitry of a storage system, an indication to selectively overwrite first data stored on a first page of a first subset of a group of multi-level memory cells of the storage system, each multi-level memory cell comprising multiple pages;

determining, using the control circuitry, in response the indication to selectively overwrite the first data, a second subset of memory cells from the first subset that, in response to programming from a first level to a second level, will alter a read output of the first data on the first page and maintain a read output of the remaining of the multiple pages; and

programming the second subset of memory cells from the first level to the second level to securely remove the first data stored on the first page while maintaining data on the remaining of the multiple pages.

19. The method of claim 18 ,

wherein the group of multi-level memory cells comprises a group of triple-level memory cells, each triple-level memory cell defining three pages and eight levels, wherein the three pages comprise a lower page, an upper page, and an extra page, and wherein the eight levels include level 0 (L0) through level 7 (L7),

wherein the first page is one of the three pages and the remaining of the multiple pages include the remaining two of the three pages, and

wherein the second level is a successive level to the first level.

20. The method of claim 18 ,

wherein the group of multi-level memory cells comprises a group of two-level memory cells, each two-level memory cell defining two pages and four levels, wherein the two pages comprise a lower page and an upper page, and wherein the four levels include level 0 (L0) through level 3 (L3),

wherein the first page is one of the two pages and the remaining of the multiple pages includes the other of the two pages, and

wherein the second level is a successive level to the first level.

21. The method of claim 18 ,

wherein the group of multi-level memory cells comprises a group of quad-level memory cells, each quad-level memory cell defining four pages and sixteen levels, wherein the four pages comprise a lower page, an upper page, an extra page, and a top page, and wherein the sixteen levels include level 0 (L0) through level 15 (L15),

wherein the first page is one of the four pages and the remaining of the multiple pages include the remaining three of the four pages, and

wherein the second level is a successive level to the first level.

22. At least one non-transitory device-readable storage medium comprising instructions that, when executed by control circuitry of a storage system, cause the storage system to perform operations comprising:

receive an indication to selectively overwrite first data stored on a first page of a first subset of a group of multi-level memory cells of the storage system, each multi-level memory cell comprising multiple pages;

determine, in response the indication to selectively overwrite the first data, a second subset of memory cells from the first subset that, in response to programming from a first level to a second level, will alter a read output of the first data on the first page and maintain a read output of the remaining of the multiple pages; and

program the second subset of memory cells from the first level to the second level to securely remove the first data stored on the first page while maintaining data on the remaining of the multiple pages.

23. The device-readable storage medium of claim 22 ,

wherein the group of multi-level memory cells comprises a group of triple-level memory cells, each triple-level memory cell defining three pages and eight levels, wherein the three pages comprise a lower page, an upper page, and an extra page, and wherein the eight levels include level 0 (L0) through level 7 (L7),

wherein the first page is one of the three pages and the remaining of the multiple pages include the remaining two of the three pages, and

wherein the second level is a successive level to the first level.

24. The device-readable storage medium of claim 22 ,

wherein the group of multi-level memory cells comprises a group of two-level memory cells, each two-level memory cell defining two pages and four levels, wherein the two pages comprise a lower page and an upper page, and wherein the four levels include level 0 (L0) through level 3 (L3),

wherein the first page is one of the two pages and the remaining of the multiple pages includes the other of the two pages, and

wherein the second level is a successive level to the first level.

25. The device-readable storage medium of claim 22 ,

wherein the group of multi-level memory cells comprises a group of quad-level memory cells, each quad-level memory cell defining four pages and sixteen levels, wherein the four pages comprise a lower page, an upper page, an extra page, and a top page, and wherein the sixteen levels include level 0 (L0) through level 15 (L15),

wherein the first page is one of the four pages and the remaining of the multiple pages include the remaining three of the four pages, and

wherein the second level is a successive level to the first level.