IP Library Granted Patent US 10,833,059
Granted Patent B2
US 10,833,059 · App. 16/213,257 · Granted Nov 10, 2020

Integrated assemblies comprising vertically-stacked decks of memory arrays

Inventor: Werner Juengling (Meridian, ID)
Assignee: Micron Technology, Inc.
H01L25/18G11C11/4085G11C11/4091H01L23/528H01L23/5226H01L23/544H01L25/0657H01L27/10805H01L27/10897H01L2223/54426H01L2223/54493H01L2225/06541H01L2225/06565
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Quick Facts
Patent No.
US 10,833,059
App. No.
16/213,257
Granted
Nov 10, 2020
Kind
B2
Abstract

Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

Claims (31)

1. An integrated assembly, comprising:

a base comprising first circuitry;

first conductive lines supported by the base and associated with the first circuitry, the first conductive lines extending along a first direction;

a deck over the base and comprising an array of memory cells;

second conductive lines supported by the deck and associated with the array of memory cells, the second conductive lines extending along a second direction substantially orthogonal to the first direction; and

vertical interconnects extending from the deck to the base and coupling the first conductive lines to the second conductive lines; each of the vertical interconnects coupling one of the first conductive lines to one of the second conductive lines; each of the second conductive lines being coupled with only one of the first conductive lines;

wherein the first and second conductive lines are on a same pitch as one another.

2. The integrated assembly of claim 1 wherein the first circuitry is sense-amplifier-circuitry, and wherein the second conductive lines are extensions of digit-lines.

3. The integrated assembly of claim 1 wherein the first circuitry is wordline-driver-circuitry, and wherein the second conductive lines are extensions of wordlines.

4. The integrated assembly of claim 1 wherein the array of memory cells is a first array of memory cells, and wherein the vertical interconnects are first vertical interconnects; and further comprising:

third conductive lines supported by the base and associated with the first circuitry;

a second array of memory cells having fourth conductive lines associated therewith; and

second vertical interconnects coupling the fourth conductive lines to the third conductive lines; each of the second vertical interconnects coupling one of the fourth conductive lines to one of the third conductive lines; each of the fourth conductive lines being coupled with only one of the third conductive lines.

5. The integrated assembly of claim 4 wherein the second array of memory cells is supported by the deck and is laterally adjacent to the first array of memory cells.

6. The integrated assembly of claim 5 wherein:

the first circuitry is sense-amplifier-circuitry;

the second conductive lines are extensions of digit-lines; and

the fourth conductive lines are extensions of digit-lines.

7. The integrated assembly of claim 5 wherein:

the first circuitry is wordline-driver-circuitry;

the second conductive lines are extensions of wordlines; and

the fourth conductive lines are extensions of wordlines.

8. The integrated assembly of claim 4 wherein the deck is a first deck; and wherein the second array of memory cells is supported by a second deck which is over the first deck.

9. The integrated assembly of claim 8 wherein:

the first circuitry is sense-amplifier-circuitry;

the second conductive lines are extensions of digit-lines; and

the fourth conductive lines are extensions of digit-lines.

10. The integrated assembly of claim 8 wherein:

the first circuitry is wordline-driver-circuitry;

the second conductive lines are extensions of wordlines; and

the fourth conductive lines are extensions of wordlines.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2018
From: JUENGLING, WERNER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047708/0285 →