IP Library Granted Patent US 11,131,705
Granted Patent B2
US 11,131,705 · App. 16/209,393 · Granted Sep 28, 2021

Allocation of test resources to perform a test of memory components

Inventors: Aswin Thiruvengadam (Folsom, CA); Sivagnanam Parthasarathy (Carlsbad, CA); Frederick Jensen (El Dorado Hills, CA)
Assignee: MICRON TECHNOLOGY, INC.
G01R31/2874G01R31/003G01R31/287G01R31/2862
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Quick Facts
Patent No.
US 11,131,705
App. No.
16/209,393
Granted
Sep 28, 2021
Kind
B2
Abstract

A request to perform a test with one or more memory components can be received. Available test resources of a test platform that is associated with memory components can be determined. The desired characteristics of the one or more memory components that are specified by the test can be determined. One or more of the available test resources of the test platform to the test can be assigned based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components of the test. Furthermore, the test can be performed with the assigned one or more of the available test resources of the test platform.

Claims (37)

1. A method comprising:

receiving, by a processing device, a request to perform a test of one or more test memory components, wherein the one or more test memory components have desired characteristics;

identifying, by the processing device, a plurality of available test sockets of a test platform, wherein each available test socket of the plurality of available test sockets comprises a respective one of a plurality of embedded memory components;

selecting, by the processing device based on characteristics of the plurality of embedded memory components matching the desired characteristics of the one or more test memory components, one or more of the plurality of available test sockets to obtain one or more selected test sockets; and

performing, by the processing device, the test using the one or more selected test sockets.

2. The method of claim 1 , wherein each available test socket of the plurality of available test sockets comprises the respective embedded memory component and a temperature control element.

3. The method of claim 2 , wherein the test corresponds to operations performed at the respective embedded memory component at a particular temperature condition applied to the respective embedded memory component by the temperature control element.

4. The method of claim 1 , wherein identifying the plurality of available test sockets of the test platform comprises:

determining a subset of test sockets of the test platform that are not being used by or reserved by a prior test at the test platform, wherein another subset of test sockets that are being used by or reserved by the prior test at the test platform are not available.

5. The method of claim 1 , wherein each of the desired characteristics comprises an indication of prior operations that have been performed with each embedded memory component of the plurality of embedded memory components and an indication of a prior temperature condition that has been applied to each embedded memory component of the plurality of embedded memory components.

6. The method of claim 1 , further comprising:

determining locations of the plurality of available test sockets, wherein the selecting is further based on the locations of the plurality of available test sockets.

7. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

receiving a request to perform a test of one or more test memory components, wherein the one or more test memory components have desired characteristics;

identifying a plurality of available test sockets of a test platform, wherein each available test socket of the plurality of available test sockets comprises a respective one of a plurality of embedded memory components;

selecting, based on characteristics of the plurality of embedded memory components matching the desired characteristics of the one or more test memory components, one or more of the plurality of available test sockets to obtain one or more selected test sockets; and

performing the test using the one or more selected test sockets.

8. The non-transitory computer readable medium of claim 7 , wherein each available test socket of the plurality of available test sockets comprises the respective embedded memory component and a temperature control element.

9. The non-transitory computer readable medium of claim 8 , wherein the test corresponds to operations performed at the respective embedded memory component at a particular temperature condition applied to the respective embedded memory component by the temperature control element.

10. The non-transitory computer readable medium of claim 7 , wherein identifying the plurality of available test sockets of the test platform further comprises:

determining a subset of test sockets of the test platform that are not being used by or reserved by a prior test at the test platform, wherein another subset of test sockets that are being used by or reserved by the prior test at the test platform are not available.

11. The non-transitory computer readable medium of claim 7 , wherein each of the desired characteristics comprises an indication of prior operations that have been performed with each embedded memory component of the plurality of embedded memory components and an indication of a prior temperature condition that has been applied to each embedded memory component of the plurality of embedded memory components.

12. The non-transitory computer readable medium of claim 7 , wherein the operations further comprise:

determining locations of the plurality of available test sockets, wherein the selecting is further based on the locations of the plurality of available test sockets.

13. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

receive a request to perform a test of one or more test memory components, wherein the one or more test memory components have desired characteristics;

identify a plurality of available test sockets of a test platform, wherein each available test socket of the plurality of available test sockets comprises a respective one of a plurality of embedded memory components;

select, based on characteristics of the plurality of embedded memory components matching the desired characteristics of the one or more test memory components, one or more of the plurality of available test sockets to obtain one or more selected test sockets; and

perform the test using the one or more selected test sockets.

14. The system of claim 13 , wherein each available test socket of the plurality of available test sockets comprises the respective embedded memory component and a temperature control element, and wherein the test corresponds to operations performed at the respective embedded memory component at a particular temperature condition applied to the respective embedded memory component by the temperature control element.

15. The system of claim 13 , wherein, to identify the plurality of available test sockets of the test platform, the processing device is to:

determine a subset of test sockets of the test platform that are not being used by or reserved by a prior test at the test platform, wherein another subset of test sockets that are being used by or reserved by the prior test at the test platform are not available.

16. The system of claim 13 , wherein each of the desired characteristics comprises an indication of prior operations that have been performed with each embedded memory component of the plurality of embedded memory components and an indication of a prior temperature condition that has been applied to each embedded memory component of the plurality of embedded memory components.

17. The system of claim 13 , wherein the processing device is further to:

determine locations of the plurality of available test sockets, wherein the selecting is further based on the locations of the plurality of available test sockets.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2018
From: THIRUVENGADAM, ASWIN; PARTHASARATHY, SIVAGNANAM; JENSEN, FREDERICK
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047670/0566 →