Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor
An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.
1. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:
a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material;
a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;
programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;
conductive vias extending elevationally through the vertically-alternating tiers in the second region; and
an elevationally-extending wall laterally between the first and second regions, the wall comprising the programmable charge storage material and the semiconductive channel material.
2. The array of claim 1 wherein the wall is laterally spaced from a row of the channel pillars and extends along the row aside multiple of the channel pillars in the row.
3. The array of claim 2 wherein the wall is parallel with the row.
4. The array of claim 2 wherein the wall is horizontally straight-linear.
5. The array of claim 1 wherein individual tiers of the control gate material are directly against the wall on a first region-side of the wall.
6. The array of claim 5 wherein the control gate material is not directly against either of the programmable charge storage material or the semiconductive channel material of the wall.
7. The array of claim 1 wherein the wall comprises laterally outer linings of the programmable charge storage material and the semiconductive channel material and a central core comprising dielectric material.
8. The array of claim 1 wherein,
the wall is a first wall; and
further comprising:
a second elevationally-extending wall comprising the programmable charge storage material and the semiconductive channel material, the second wall angling relative to the first wall.
9. The array of claim 8 wherein the second wall joins with the first wall and comprises an angling extension of the first wall.
10. The array of claim 1 wherein the wall is vertical or within 10° of vertical.
11. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:
a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material;
a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;
programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;
conductive vias extending elevationally through the vertically-alternating tiers in the second region; and
an elevationally-extending wall completely encircling an island comprising the conductive vias, the wall comprising the programmable charge storage material and the semiconductive channel material.
12. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:
a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material;
a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;
programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;
conductive vias extending elevationally through the vertically-alternating tiers in the second region; and
an elevationally-extending wall laterally between the first and second regions, the wall being laterally spaced from a row of the channel pillars and extending along the row aside multiple of the channel pillars in the row.
13. The array of claim 12 wherein the wall is parallel with the row.
14. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:
a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material;
a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;
programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;
conductive vias extending elevationally through the vertically-alternating tiers in the second region; and
an elevationally-extending wall completely encircling an island comprising the conductive vias, the wall being laterally spaced from a row of the channel pillars and including a portion extending along the row aside multiple of the channel pillars in the row.
15. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:
a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material;
a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;
programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;
conductive vias extending elevationally through the vertically-alternating tiers in the second region; and
an elevationally-extending wall in the second region, the wall being laterally spaced from a row of the channel pillars and being longitudinally elongated at an angle relative to the row.
16. The array of claim 15 wherein the wall is longitudinally elongated orthogonally relative to the row.
17. The array of claim 15 wherein the wall comprises the programmable charge storage material and the semiconductive channel material.